Authors: a. glascott Jones, M. wingender, n. chantier, G. thepaut, J. P. Amblard, e. marcelot, e2v
The use of analog-to-digital converter (ADC) is becoming more and more popular in frequency domain applications such as radar and direct down conversion receiver. For these high frequency applications, dynamic range and background noise are particularly important, which also provides impetus for the promotion of 12 bit ADC. The attraction of directly generating transmission signal and directly converting received signal without external down converter is obvious, because this scheme has the advantages of flexibility and reducing the number of components. This is particularly important in aerospace applications where constraints such as area and power consumption are critical.
For a long time, this kind of direct frequency conversion without mixer has been the dream product of system architects. Now with the development of semiconductor technology, we can see that many commercial components can be used to realize this kind of system in more applications. This paper discusses the characteristics of frequency converter for high frequency applications, including flat frequency response, high input bandwidth, low input full scale voltage range and the ability to adjust parameters for multi array systems. The system design considerations related to the selection of high resolution and high speed ADC are also discussed.
Direct down conversion architecture
Direct down conversion receiver is more and more popular in practical communication system and radar application. Applications such as communication satellite repeaters and synthetic aperture radar earth observation systems can benefit greatly from the use of complete direct frequency conversion transceivers. This technique allows direct digitization of the entire pulsed RF spectrum, further enhancing the bandwidth of interest that can be observed in a fast Fourier transform (FFT) scan, thus bringing greater flexibility to receiver performance. In this case, a single ADC can replace multiple channels of traditional if down conversion.
L-band (1GHz to 2GHz) has excellent weather penetration capability, so it has many applications, including communication satellite repeater, synthetic aperture radar (SAR) earth observation system, military space surveillance, missile detection and guidance, and clear sky troposphere observation.
Remote detection of SAR is a very interesting application, which uses the relative motion between the antenna and its target area to perform terrain imaging. In this kind of application, high resolution, high linearity and the ability to adjust the phase of sampling points accurately are very important. Electronic warfare (EW) system requires high sampling rate, the ability to scan as wide as bandwidth and low delay, so as to capture data quickly.
The application of multi array beamforming allows to improve the gain of a particular signal or reduce the influence of blocking or interference signals by selecting the direction. In this case, the phase control function is very important, as shown in Figure 1.
Figure 1: antenna array receiver system.
Single core ADC
For the ADC used in L-band applications, two key indicators are very important, namely spectrum purity and background noise.
The real single core architecture has great advantages, because it can achieve 1.5gs/s update rate without internal alternation. Therefore, calibration is not required before or during operation in the extended temperature range（ One of the characteristics of alternating ADC is that it has significant alternating pulses. Offset mismatch will produce a fixed frequency pulse. However, gain and phase mismatch will produce spurious frequency depending on the input signal frequency. In fact, the use of internally alternating ADCs often requires calibration to avoid spurious free dynamic range performance degradation due to gain, offset, and sampling aperture delay mismatches.
From the spectrum purity diagram shown in Figure 2, we can see the advantages of single core. The selection of frequency should make the main signal and its harmonics close together in FFT diagram. This allows the rest of the spectrum to freely display spurious signals associated with any other non signal, such as clock pulses. The alternating ADC may be able to display pulses in this region, but we can see that the single core has no spurious region and 90dbc spectral purity.
Single core architecture also has advantages in latency. For example, the delay of ev12as200 can be as low as three clock cycles, which is very useful in applications such as electronic warfare and tracking system.
Figure 2: spectrum purity diagram of ev12as200.
The factor behind the SNR of high bandwidth ADC can be determined by the following formula:
Where nqi is the ideal quantization noise Q / √ 12 and NQD is the deviation from the ideal (DNL). Nthermal is the hot white noise, njitter is the total jitter value, which is composed of internal ADC jitter and external clock jitter.
If the internal clock jitter is about 100fs RMS, it means that the external clock should be selected to achieve at least this jitter value of the system. Ideally, smaller jitter can achieve the best performance. The following table shows an example of calculating the noise performance according to the ev12as200 ADC index.
Table 1: typical background noise calculation.
Another important consideration in L-band applications is that the performance should be stable up to the end of the second Nyquist region. This also implies that the bandwidth should cover this area, and the performance parameters such as SFDR, third-order intermodulation index and significant bit (ENOB) should be kept flat (see Figure 3).
Figure 3: significant bit values of ev12as200.
Since multi array design is an important application of this type of ADC, the ADC should be able to match other ADCs in the array. Therefore, gain, offset and phase should have adjustment function. For example, the functions described below are ideal:
ADC gain control: fine tuning（ ± 5%), using 10 bit DAC（ ± 0.5 LSB）
ADC offset control: fine tuning（ ± 5%), using 10 bit DAC（ ± 0.5 LSB）
ADC sampling delay adjustment: 30ps fine tuning range, 10 bit DAC: 30fs step
These functions can also be used to alternate multiple 12 bit ADCs (to increase the actual sampling rate). In addition, the synchronization function of aligning multiple channels during initialization is also very important. This function can also be shared with the trigger function, allowing external digital input and analog data to achieve time synchronization.
Because the output data rate will be close to the limit of internal FPGA, an important function is to demultiplex (dmux) the data to reduce the data speed at the cost of introducing more output ports（ Ev12as200 provides 1:2 dmux solution)
Another important function is the input voltage full scale range. The harmonic performance of ADC is so low that the bad spurious level of input driver will seriously affect the system performance. If the ADC can accept low input voltage, then this problem can be alleviated. The input voltage range of ev12as200 is 500mvpp.
The choice of clock source and driving system is very important, because jitter is a major factor in calculating the total noise. In order to achieve the best performance, the jitter of about 100fs is ideal. This means that the source phase noise is 150dbc / Hz or less, and the additional jitter of any clock buffer is much less than 100fs.
PCB tracking is also the key point. Analog tracking should match the source (or load) to get a VSWR close to 1. Digital tracking should match to 100 Ω Impedance and length should be matched better than ± 2.5mm to ensure that the swing rate deviation of the interface FPGA will not be too large. FPGA interface is also a complex part of the system. In order to achieve high data rate, it may be necessary to extend the SerDes unit inside the application.
The system performance can be further enhanced by post-processing and real-time techniques, such as integral nonlinearity (inl) correction and high frequency vibration (dither) to improve SFDR.
The shape of inl curve has a great influence on the harmonic performance of ADC. By characterizing the inl and using the LUT in the interface FPGA, the inl can be minimized and the SFDR performance can be improved. Look up table correction is a simple way to subtract or increase the inl value of measurement code. Using this technology has little impact on the scale of FPGA and no impact on the throughput. In many cases, adding a look-up table for inl correction can improve the SFDR performance by 10dB.
Adding an out of band noise source to the input data can also improve the SFDR performance. This can be a simple noise generator after low-pass filtering, which is added to the input signal by using a multi port transformer. The effect is to move the input signal within the ADC input range, which is conducive to reducing the inl effect and improving the SFDR (see Figure 4).
Figure 4: using high frequency vibration to improve SFDR.
The spectrum in the upper part of Figure 4 shows the harmonics without additional jitter, while the spectrum in the lower part shows the harmonics with high frequency vibration. It can be seen that the stray harmonics are significantly reduced.
About the author
Andrew glascott Jones is an application engineer in the mixed signal ASIC Business Department of e2v company in Grenoble, France. Andrew has nearly 25 years of experience in the field of electronic measurement system design, including precision measurement, particle size adjustment, X-ray imaging and laser spectroscopy. E2v’s mixed signal ASIC business unit mainly designs and provides customized ICs for sensor interface applications in automotive, industrial and medical markets. Andrew is responsible for the development kits provided by e2v company, and provides help to customers in ASIC development phase. These packages provide i.p. module examples to help customers demonstrate proof of concept early in the design cycle and efficiently pre develop complete ASICs.
Editor in charge: GT