This paper introduces a scheme of scan controller based on FPGA programmable logic device, which uses large screen full-color LED display screen to display full-color gray image. After “19” Based on the analysis of the gray realization principle of “field scan” theory, aiming at the shortcoming that the refresh frequency of full-color LED display is limited by serial shift clock, a new bit by bit lighting control method for high-level gray-scale display is proposed. In the FPGA circuit design, a separate counter is used to control the refresh frequency of the screen, so that the full-color LED display screen is designed in the LED The adjustment between luminous efficiency and refresh rate is more flexible. Finally, according to the design requirements of large screen full-color LED display, combined with the gray control method discussed in this paper, the internal circuit implementation framework of FPGA screen scan controller is given.
As a kind of large flat panel display equipment, LED display plays an important role in the display field because of its long service life, low maintenance cost and low power consumption. Especially in recent years, the full-color LED display with red, green, blue and gray display effect has attracted the attention of the industry for its rich and colorful display effect, and has become a product with a relatively large growth rate in the LED display market in recent years. The performance of the indicators such as life, unit area brightness, deviation degree of three basic colors, point distance, contrast, gray level (including gray scale series and linearity), scanning frequency and so on are the standards for measuring or comparing the quality of large-scale display equipment horizontally. The performance of these indexes is largely determined by the performance of the scan controller. Therefore, it is of great significance to study the scanning control method of large screen full color LED display.
Because the brightness of LED is approximately proportional to the luminous time in the scanning period, the gray level is usually realized by controlling the ratio of the LED luminous time to the scanning period, that is, by adjusting the duty cycle. The full-color LED display screen generally adopts the scanning mode of bit by bit lighting to realize the gray image display. For the LED display with 8-bit gray level, the principle of “19 field scanning” is generally used to realize 256 level gray level display. The display data of LED display screen is usually updated by serial output. For example, the static LED full-color display screen designed with 595 is adopted. According to the principle of “19 field scanning”, when the serial shift clock is determined, the refresh frequency of the display screen and the luminous efficiency of the LED (the proportion of the longest lighting time of the LED in a scanning cycle) are determined And it was confirmed. This paper presents a new bit by bit scanning mode, which improves the typical “19 field scanning” mode. It can adjust the refresh rate and luminous efficiency within a certain range under the condition of determining the serial shift clock, so as to improve the flexibility of the product design according to the actual application environment and customer requirements.
2. Design of gray level realization algorithm based on bit by bit lighting
Taking the 8-bit “19 field scanning” theory as an example, the so-called bit by bit lighting means that one bit data is extracted from a byte data in turn from low bit to high bit or from high bit to low bit, and the corresponding pixel is illuminated in eight times. The duty cycle of each bit corresponding to the lighting time and turn off time is different. If the lighting time is multiplied from low to high, there will be 256 kinds of combination of lighting time. Define the lighting time corresponding to d0 bit and turn off time as a time unit, and set it as t to get the lighting and turning off time of each bit as shown in Table 1.
Table 1 lighting and turning off time of each member in “19 field scanning” display
In the actual design, t is also the time needed to update the serial data of LED display. The total time shown in Table 1 is an integral multiple of T, so the total time consumed by each data bit can be timed by refreshing the screen data once. In the design of LED display screen, the light and off of LED in the whole display screen can be controlled by the main control line en. When the lighting time is more than 1 T, the en control display screen is in the normal light state. When the lighting time is 1 T, the corresponding position brightness control can be realized by controlling the en to generate the corresponding duty cycle control waveform. It can be seen that by using the principle of “19 field scanning”, when the serial shift clock and the specific specifications of the screen are determined, the refresh rate is also determined, and the luminous efficiency η is fixed.
(1) according to the principle of gray scale display, whether the gray display can be realized depends on whether the lighting time of each data bit increases by a multiple of 2 from the low bit to the high bit, and the length of the off time only affects the luminous efficiency. In the system design, 8-10 bit nonlinear gray correction is used, so it is necessary to realize 10 bit gray level scanning control. If “t” is defined as a time unit of lighting time, the time distribution shown in Table 2 can be obtained. When the input data changes from 000h to 3ffh, the lighting time varies from 0t to 1023t, and the total brightness control time remains unchanged. Thus, the 10 bit duty cycle control is realized. The gray level display of 1024 level can be realized by using this gray control method. Different from the principle of “19 field scanning”, the control of lighting time in this paper is not realized by screen refresh, but by using a separate counter for timing control.
Table 2 data lighting time distribution table in bit by bit lighting control
Set the time required to update one bit data of the whole video image in serial mode as ts. if TS meets the following requirements:
Then the time required to complete a serial data update is between the lighting time of DN – 1 bit and that of DN bit, which may be less than a time t. Since the serial data update time and the lighting time can be partially overlapped, if the refresh rate of the screen (that is, the frequency of the display data frame read out from the display buffer for screen display update) is f r, equation (3) can be obtained.
When the serial clock frequency and screen parameters are determined, ts can be calculated. At this time, if the refresh rate of the screen is set, the n value satisfying the conditions of both formulas can be obtained by exhaustive calculation of N from 0 to 9 by combining formula (2) and equation (3), and the value of unit time t can be determined. The T value obtained by this method can be controlled by FPGA, and the full-color gray level control with a certain refresh rate can be realized.
Here, the luminous efficiency of LED can be expressed by formula (4).
It can be seen from equation (3) that when the serial shift clock frequency is fixed, that is, TS is determined, the refresh rate f r is inversely proportional to the unit time t. Formula (4) shows that the luminous efficiency η is directly proportional to the unit time t. It can be seen that there is an inverse relationship between the refresh rate and the luminous efficiency. Therefore, with the above scanning method, the designer can adjust the refresh rate and luminous efficiency according to the actual application environment and customer requirements.
If the full-color gray control of the system is required to conform to the display effect of “19 field principle”, the values of turn off time t0-t9 shown in Table 3 can be obtained from table 2. Combined with the values of t0-t9 in Table 3, the total time items in Table 2 are summed, and the total time is ta = 1 152t. According to 1 152t = 1 / f r, t value can be obtained.
Table 3 turn off time allocation table of each data in bit by bit lighting control in accordance with “19 field scanning”. In the system design, each output port of the scanning board controls the static display module with 16 × 48 resolution. The red, green and blue display data are respectively output by three data lines. The serial shift clock frequency is 6.25 MHz, and the display refresh frequency is 120 Hz Based on the above conclusions, we can draw the following conclusions
TS = 16 × 48 × 16125 × 106 s = 122188 μ s, and then exhaustive calculation is carried out. As shown in Table 4, the value of unit time t is 7.780 μ s.
According to formula (4), the luminous efficiency η = 1023tf, r = 1023 × 71780 × 10 – 6 s × 120Hz = 9515%
3. FPGA circuit design
Because of the high frequency of video image signal and the large amount of data, real-time processing is required. In addition, the digital logic of full-color large screen LED controller is quite complex. The control circuit designed by CPLD / FPGA can simplify the system structure and facilitate debugging. The scanning controller designed in this paper is applied to large screen full-color LED offline video playback system. It involves the storage and reading of video signal, transmission and reception of video data, gray display control circuit, LED dot matrix display drive circuit and so on. This paper mainly discusses the gray level display control circuit. The control object is the full-color static display screen composed of red, green and blue LEDs. The FPGA internal circuit structure of gray display controller is shown in Fig. 1.
FPGA is the most important logic control device in the LED display scanning control circuit, which mainly realizes the functions of video data receiving, nonlinear gray correction and scanning signal generation. The internal circuit modules of fp2ga work coordinately with each other to connect the data input and display output to realize the full-color Video playback of LED display screen.
As an independent display system, ordinary RS232 and RS485 bus can not meet the high data rate transmission requirements of LED display screen for multimedia video playback. Taking 512 × 256 full-color display screen as an example, when the frame changing frequency of the system is required to reach 30 Hz, the required data transmission rate is as high as 94.4 Mbps. Therefore, in the system design, the transmission and reception of video data is completed by using the 100 m Ethernet controller designed by rtl8201.
In order to make the video play continuously and smoothly, the display cannot be interrupted during the data receiving process. Here, two groups of SRAM are used for “ping pong operation”, so that the receiving storage and reading of display data can be carried out at the same time, so as to realize seamless buffering and processing of video data stream, as shown in Fig. 2. Frame_ Switch is used to switch working SRAM groups. The signal determines which SRAM group is in read state and which group is in write state. The data receiving module of rtl8201 establishes the MII interface, realizes the interface with rtl8201, converts the half byte data transmitted by MII interface into 24 bit RGB data, and then stores it in SRAM. When rtl8201 receives a frame of display data, the frame is exchanged_ Switch reverses and switches the reading and writing positions of the two groups of SRAM, so that the display screen displays the latest received frame data, so as to realize the frame exchange operation.
As the LED display screen contains four columns of independent display modules, the scanning control circuit needs to provide four channels of RGB data output interface, which are represented as rgb0 ~ rgb3 in Figure 1.
CLOCK_ Out is the output port of shift clock signal. Rgb0-rgb3 is effective on the rising edge of the clock. The red, green and blue display data of each port are moved into the display buffer of the driver chip bit by bit through the clock pulse signal. The latch signal is the latch pulse when the display refresh is needed after the serial data output. EN is a gray control signal. When en is valid, LED can be off or on with the 0 and 1 status of input data, and its effective time width corresponds to the lighting time shown in Table 2.
EN signal generation module is an important module for gray image display. The module converts the input bit count value into the corresponding bit lighting time, and controls the brightness of the corresponding time length.
In this design, the input gray signal is 256 levels. Considering the gray loss caused by the anti gamma nonlinear correction process, the output gray level is defined as 1024 level. Therefore, it is necessary to obtain the corresponding lighting time of each bit of 10 bit gray data. According to the “gray realization principle”, the corresponding lighting time of each data bit of 10 bit gray data is multiplied from 1 t to 512 t from d0 to D9, and the total lighting time is 1 023 t.
Since the driver chip in the driver board has the function of two-level buffer, the two control processes of updating data and lighting LED can be partially overlapped, thus obtaining the gray control flow of LED display shown in Fig. 3. When updating bit 0 data, the lighting time is 512 T, and when updating the first bit data, the lighting time is 1 t. … in turn, when updating the n-th bit data, the control lighting time is the lighting time required by the last updated bit.
This paper discusses the design scheme of scanning controller for large screen full-color LED display screen. Through the analysis of the implementation method of “19 field scanning”, aiming at its shortcomings, a new control method of bit by bit lighting gray level is proposed. This control method makes it possible to flexibly adjust the luminous efficiency and refresh rate of LED in the design of full-color LED display. This design uses fp2ga control chip as the design platform to complete the realization of the scanning control circuit. With the help of EDA development tools, it reduces the design difficulty of the drive circuit and shortens the development cycle of the project.