Concept of power integrity
Power integrity (PI) is to provide a stable and reliable power distribution system (PDS) for board level system. In essence, it is to effectively control the power and ground noise when the system is working, provide sufficient energy for the chip in a wide frequency band, and fully suppress the voltage fluctuation, radiation and crosstalk caused by the chip working.
With the development of VLSI technology, the working voltage of the chip is lower and lower, the working speed is faster and faster, the power consumption is higher and higher, and the density of the single board is higher and higher. Therefore, higher requirements are put forward for the stability of the power supply system in the whole working frequency band. The level of power integrity design directly affects the performance of the system, such as the reliability of the whole machine, SNR and BER, EMI / EMC and other important indicators. The high impedance of board level power supply channel and the excessive SSN of synchronous switching noise will bring serious power integrity problems, which will have a fatal impact on the stability of devices and systems. PI design is to ensure that the impedance of board level power supply channel meets the requirements, the quality of board level power supply meets the requirements of devices and products, and the signal quality and stable operation of devices and products through reasonable plane capacitance, discrete capacitance and plane division application.
Interaction between power integrity PI and signal integrity Si: from the perspective of the whole simulation field, at the beginning, everyone focused on signal integrity, but in fact, power integrity and signal integrity interact and restrict each other. The power supply and ground plane provide the reference circuit for the signal line while supplying power, which directly determines the return path, thus affecting the integrity of the signal; Similarly, different signal integrity processing methods will bring different impacts to the power supply system, and then affect the integrity design of the power supply. Therefore, it is very beneficial to integrate power integrity and signal integrity. After the design engineer has mastered the signal integrity design method, it is necessary to enrich the power integrity design knowledge.
Content of power integrity research: there are many contents of Power Integrity simulation, but the main aspects are as follows:
1: Based on the full use of planar capacitors, the number, type and location of bypass capacitors are determined by simulation analysis to ensure that the impedance of board level power supply channel meets the requirements of stable operation of devices.
2: The board level DC voltage drop simulation analysis ensures that the board level power channel meets the voltage drop limit requirements of the device.
3: Board level resonance analysis can avoid the fatal impact of board level resonance on power quality and EMI.
Power distribution system
Power distribution system (PDS): the figure above is a classic power distribution system characteristic diagram, I believe everyone is familiar with it. From this picture, we can divide the whole power band into several parts. In the low frequency band, the power noise is mainly filtered by the power conversion chip VRM. In the frequency band from a few MHz to a few hundred MHz, the power noise is mainly filtered by the board level discrete capacitor and the power ground plane pair of PCB. In the high frequency part, the power noise is mainly filtered by the power ground plane of PCB and the high frequency capacitor inside the chip. When we do the simulation, the simulation accuracy of the low-frequency and high-frequency parts is not accurate. The really meaningful frequency band is mainly in the frequency band of several MHz to several hundred MHz.
Target impedance ztarget
Target impedance is a useful but imprecise criterion in Power Integrity simulation.
Where: ztarget target impedance
Power supply voltage is the operating voltage
Allowed ripple is the allowable operating voltage ripple coefficient
Current is the working current. At present, this value is replaced by 1 / 2 of the maximum current
As we all know, when testing the power supply, it is mainly to test the ripple and noise. However, it is difficult for the industry to simulate the ripple and noise in the time domain through software (some large companies have built the noise model of the chip through testing, and then directly simulate it with this model. The result is the power supply noise, but it is still in the exploratory stage, and has not been widely used), It is to simulate the power impedance of the power distribution system, and their relationship can be connected by V = R / I. Therefore, if the impedance curve is simulated, the test and simulation can not form a closed loop.
When measuring whether the impedance curve can meet the requirements, the target impedance standard is used. However, if you think about it carefully, there are still many problems in this standard, such as: how appropriate is the current here? The actual power consumption of single board is a dynamic power consumption, which is variable. It is certainly unreasonable to use a unified target impedance value in the whole frequency range of a single board. It should be different frequency bands and different standards.
Although there are these problems, but this standard is still very useful, we can use this standard to measure the quality of the power plane. Just like the current time series calculation, we basically calculate the time series through the formula, which is the so-called static time series analysis. Although the static timing analysis does not consider the power fluctuation, ISI, SSN and other issues carefully, that is to say, the calculation results are not accurate, it is very useful to measure the interface timing. Therefore, target impedance is a useful and inaccurate standard.
Capacitance is not just capacitance: when the frequency is very high, capacitance can no longer be regarded as an ideal capacitance, but its parasitic parameter effect should be fully considered. Usually, the parasitic parameters of capacitance are ESR and ESL. The RLC circuit in series resonates at F. The curve is shown in the figure below. In the figure, f is the series resonant frequency (SRF), which is capacitive before F and inductive after F, which is equivalent to an inductor. Therefore, when selecting the filter capacitor, the capacitor must work before the resonant frequency.
In the simulation, due to the current VRM model is basically inaccurate, low-frequency filtering is completed by DC / DC power conversion chip, generally the low-frequency impedance curve below 300K is inaccurate. The upper limit of the frequency range is usually taken as the cut-off frequency fknee = 0.35/trrise, where trise is the rise time of the signal.
But also understand that if you only do Board Level Power Integrity simulation, you can consider 1g at most, because after 1g, it depends on the internal capacitance of the chip to filter. When doing board level simulation, there is no internal model of the chip, so the simulation of the high frequency part is not accurate. Of course, if you have the information inside the chip, you can also use siwave and other software to do the collaborative simulation of die-package-board, and the high-frequency part will be accurate.
Therefore, in many cases, the low-frequency simulation can’t get the negative feedback of power supply, and the high-frequency simulation can’t get the capacitance in the chip. We don’t take the simulation result as the absolute value, we can take it as the relative value, and optimize the impedance through the selection and placement of decoupling capacitance, the segmentation of power supply and ground plane, etc. Therefore, when doing simulation, we need to use it flexibly.