introduction

With the popularity of consumer products such as PDA, mobile phone, digital camera and printer, the high-speed data transmission technology between these devices and computers or between devices has attracted more and more attention. In the past, the data transmission structure with computer as the core is very unfavorable to the application of USB bus in embedded industry and field operation. However, the introduction of OTG technology can realize the data transmission between devices without PC, which expands the application scope of USB technology. The design scheme adopted in this paper is based on ISP1362 OTG control chip of Philips company. Referring to the latest USB OTG technical specification, a master / slave system following USB protocol is designed.

1 internal structure of ISP1362 chip

ISP1362 of Philips company is an interface chip conforming to USB 2.0 bus protocol. There are three USB controllers inside, i.e. host controller, device controller and OTG controller. The host controller has highly optimized USB host function; The device controller has up to 14 programmable endpoints and can be configured as double buffered endpoints to further improve throughput: the OTG controller mainly provides all OTG controls including monitoring and conversion functions. The internal structure of ISP1362 is shown in Figure 1.

Referring to USB OTG technical specification, a master / slave system following USB protocol is designed

2 USB OTG master / slave system design

The design of USB OTG master / slave system includes two modules: hardware design and software design. The hardware circuit is mainly the design of USB interface circuit board; Software design includes device initialization, system function design, device driver design, etc. the following describes the design methods of system software and hardware system respectively.

2.1 system hardware circuit design

The hardware circuit of USB OTG master / slave is shown in Figure 2. In the figure, the PD port and IPA port of Atmega 32 are used to control the timing of ISP1362, and the Pb port and PC port are used to exchange data with D [0.. 15] of ISP1362. ISP1362 chip has two USB interfaces, port1 and iport2. Port1 is a comprehensive interface, which can be configured as downstream, upstream or OTG; Port2 is a fixed downstream, mainly connected to general USB devices. When ISP1362 is the host, the internal register of the host can judge whether port1 or port2 is connected to the device by detecting the value of its corresponding status register, so as to carry out corresponding processing.

Referring to USB OTG technical specification, a master / slave system following USB protocol is designed

The master / slave function of port 1 of ISP1362 is determined by the combination of ID and otgmode pin levels. When the otgmode pin is connected low, regardless of the ID level, the port1 port of the chip can only be used by OTG; If the otgmode is connected high and the ID is connected low, the port1 port of the chip is used as the host; When the otgmode is connected high and the ID is also connected high, the port1 port of the chip is used as a peripheral. In the circuit, the level changes of ID and otgmode pins are realized by 15K Ω pull-up resistance and pull-down resistance.

2.2 system software design

The host system of this design is a collection of software and hardware. The realization of the function does not depend on any operating system, but schedules various tasks through interruption to meet the requirements of USB communication. Therefore, the system runs according to the protocol specification and specific timing.

The system is an application of ISP1362 working in master / slave mode. The interface chip is configured according to the system hardware circuit, and then programmed to carry out USB data transmission. The system workflow is as follows: first, initialize the system, build PTD transmission descriptor, then the bus enumeration process, assign addresses to peripherals, obtain the basic information of peripherals, judge whether peripherals are host devices or slave devices, then drive the corresponding master / slave drivers to run, transmit and receive data, and judge whether to hang according to the activity of the bus. The system flow chart is shown in Figure 3:

Referring to USB OTG technical specification, a master / slave system following USB protocol is designed

To realize the software programming control of ISP1362 chip is to control the CS, RD, WR, A0 and A1 pins of the chip. In this paper, CS represents chip selection, and low level is effective; Rd stands for read signal, low level is valid; WR stands for write signal, and low level is valid; A0 pin level is different, indicating whether the transmitted signal represents command signal or data signal; The level of A1 pin is different, which indicates whether the control is peripheral or host. Through the combination of the above pin signals, different functions of read-write control ISP1362 can be realized. In addition, the following pins are also of great significance for controlling ISP1362: dreq1 pin represents DMA request output. When its high level is valid, it notifies IDMA controller that the host is requesting data transmission; When the dreq2 pin high level is valid, notify the DMA controller that the peripheral is requesting data transfer; Dack1 pin represents DMA confirmation input. When the low level is valid, it indicates that the DMA transfer request from the host has been confirmed by the DMA controller; When the low level of dack2 pin is valid, it indicates that the DMA transmission request from the peripheral has been confirmed by the DMA controller; The INT1 and INT2 pins are connected to the IRQ pin of the external microprocessor so that ISP1362 can execute the interrupt service program upon request. The specific work flow of software design is as follows:

(1) System hardware initialization, including Atmega32 and ISP1362 initialization. AVR microprocessor is an 8-bit embedded RISC processor of ATMEL company. It has the advantages of low power consumption, high speed, high output, open development tools and high cost performance. Its program memory and data memory are Harvard structures that can be accessed independently, so the code execution efficiency is very high. The internal modules of Atmega Series MCU are still very rich, and there are many available resources. The initialization of Atmega32 in this paper is to set its I / O port, timer, clock, watchdog and so on to make it work. The initialization of ISP1362 is that after ISP1362 is powered on, the host controller driver (HCD) must configure the host controller through a series of hardware initialization steps to enter the operable state. First, check whether the host controller exists. This step is realized by MCU (single chip microcomputer). This paper writes a value in the hcscratch register through MCL, and then reads it from the register. Compare the read value with the written value. If it is equal, it indicates that the host controller exists; Otherwise, an error occurs and no host controller exists.

(2) Build PTD descriptor. PTD (phi l IPS transfer descriptor) provides a transmission channel for the communication between ISP1362 host controller and peripherals. To communicate between host and peripherals, a PTD needs to be constructed first. PTD has three transmission types: control and batch transmission (aperiodic transmission) PTD, interrupt transmission PTD and synchronous transmission PTD.

(3) The host assigns an address to the device and obtains the device descriptor and device function information. The host obtains the function information of the device and endpoint by constantly sending device requests to the external device. The process of obtaining USB device descriptor is divided into three steps: a. the host obtains the device descriptor through the default endpoint of the device and assigns a unique address to the device; b. The host reads configuration descriptor information, interface descriptor information and endpoint descriptor information; c. Call the corresponding transaction handler according to the relevant information of the device.

(4) After the device enumeration is successful, the host can conduct USB communication with peripherals according to the written process, waiting for and querying the sending and receiving of data.

(5) After the data is sent or received, query the activity of the bus according to the querybus function to determine whether the device needs to be suspended.

2.3 device drivers

In order to read and write from the host to the slave, the USB host must have corresponding drivers to encapsulate, interpret and execute various read and write instructions. There are many ways to develop the driver. In this paper, a USB transmission API function usbxfer is directly encapsulated in the upper layer of the USB host interface driver, which is applied to realize various USB transmission.

3 conclusion

The USB 0tg master-slave system designed in this paper has stable performance and high data transmission efficiency. The test shows that this design can correctly realize the data exchange between USB 0tg master and slave, the performance can meet the data transmission requirements between devices, and can well control the cost, so it has a certain practical value.

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