Trends in end applications show that OEMs are still pursuing higher speed and resolution, lower distortion, loss, smaller size and lower cost. However, converter designers have not developed a new architecture to meet these needs of customers, and in fact, few designers do so. On the contrary, the development of the existing architecture has far exceeded the imagination of its inventors and continues to develop rapidly in a highly competitive field of the IC industry.

trend

This development has been very rapid. For example, in the latest high-speed ADC survey of EDN magazine, the fastest 12 bit converter being sold is ad9433 of analog devices. The operating speed of ad9433 is 125ms / s, the power is 1.25W and the bandwidth is 750MHz. In our current survey, at least five manufacturers have provided devices with a speed range of 125ms / S ~ 1gs / s, and the resolution is related to the speed, ranging from 8 bits to 14 bits.

In the previous survey, the fastest converters are mostly based on SAR (successive approximation register) architecture or pipeline architecture. It has long been a high-speed research topic in universities Δ-Σ Structure is beginning to fill the gap left by SAR in the commercial market.

As manufacturers “strive to be the first” at a rapid speed, the speed of product launch seems to be accelerating. Unfortunately, in the quarters after the product launch, the manufacturers provided only some preliminary data sheets. Preliminary data sheets are not just bad. In fact, they help IC manufacturers and early adopters start working together faster. However, some data sheets have multiple revisions (sometimes more than 8), which makes it difficult for people to design in an error free way when obtaining IC samples.

On the other hand, the specification games that manufacturers often play are less popular, at least less obvious, than in the past few years. Most data sheets specify the minimum and maximum performance limits for the most important parameters, and some specify these limits over the entire operating temperature range of the IC. The minimum ENOB (number of significant bits) specification is common, but it is still not common. In the absence of specifications, you can directly calculate ENOB from the lowest SINAD:

The AC characteristics of the converter are a challenge for medium speed communication, especially at RF (see the attachment “single value paradox”). If you don’t have rich knowledge of high-speed converters, you should spend more time on converter selection. There are many subtle differences between converters with similar speed and resolution. As a result, the length of the data table is often close to

Where l is the length, f is the clock rate, and M is the variable related to the manufacturer. In this category, only a few devices have direct equivalents from the second source. For manufacturers, a more common tendency is to provide pin compatible “upgrade paths” that enable you to migrate a design to a higher resolution or clock rate.

With the maturity of basic technology and circuit technology, as well as the expansion of market scale and intensified competition in the field of high-speed converters, the specifications provided by major manufacturers have become more stringent. For example, a brief study of data tables shows that static errors are generally small. The maximum DNL (differential nonlinearity) is usually less than 1lsb. As a result, the manufacturer guarantees not to lose the resolution of the code, which is generally equal to that on the nameplate, with very few exceptions. Inl (integral nonlinearity) is also usually less than 1 LSB, exceeding a few LSBs in only a few devices. High static performance is accompanied by high AC performance, which is due to the relationship between static nonlinearity and distortion. Therefore, noise dominates the ENOB of many converters. The data sheets of most High-Speed ADCs show that the SNR and SINAD (signal, noise and distortion) specifications differ by only one tenth or a few tenths of a decibel. In this case, if the data sheet does not specify the worst-case ENOB or SINAD, you may be able to reasonably estimate SINAD by combining SNR and separately reported distortion information. However, you should be very careful if your estimate includes typical values, especially when your estimate is close to the minimum requirements of the application.

As already mentioned, IC manufacturers often want to outperform other companies and claim that their converters are the fastest. At a specific resolution, most applications do not need the fastest converter on the market, but only fast enough converters. As long as the converter manufacturer can meet the speed needs of your design, in terms of direct use, further speed improvement may not be as good as gradually improving ENOB, power consumption or cost. These features show a rich diversity in the field of available devices.

Most high-speed converter manufacturers can provide a wide range of layout information and recommendations for buffer amplifiers suitable for various applications. Most manufacturers also provide evaluation boards so that you can start the design work quickly and use them as a comparison point later in the design cycle. Despite this high level of application support, you must carefully minimize the interaction between the converter and other nearby sub circuits.

successive approximation

Typical SAR converters released in the past few quarters are about twice as fast as the devices discussed in reference 1. Using the product of ENOB and the maximum sampling rate as the quality factor, the products with outstanding performance include ads7881 of Texas Instruments, ad7621 of analog devices and ltc1403a of linear technology (Table 1).

Preventing application front-end collision based on SAR converter

Analog’s 16 bit ad7621 provides three working modes, plus “power saving mode”. In the so-called warping mode (for applications with insufficient sampling), ad7621 can sample 2.5m times per second. It is worth reminding that the interval between continuous conversions should not exceed 1 ms. If the conversion does not meet this criterion, such as at the beginning of a burst conversion or after a power on sequence, you should ignore the first conversion. The normal working mode of ad7621 does not require the minimum conversion rate, and the operating speed is 2ms / s. There is also a low-power mode, which is called pulse mode by fans of Star Trek of analog devices. The power consumption is adjusted according to the sampling rate, and the maximum rate is 1.25ms/s. According to the latest preliminary information, the company has not released the “traction beam” option, so you must solder the LQFP-48 or optional lfcsp-48 package to the printed circuit board, just as you do for all other devices.

Ad7621 relies on a single 2.5V supply voltage to work, with on-chip low drift reference, reference buffer and temperature sensor. If you use the converter with an external input selector, the converter can measure its own temperature, so you can use this data to improve the calibration accuracy over the entire operating temperature range.

The working speed of the 14 bit ltc1403a converter of linear technology is 2.8ms/s, the power consumption is only 21mw, and the power supply voltage is 3V. In fact, among the recently launched SAR converters, ltc1403a and its sister product 12 bit ltc1403 have the highest energy efficiency among single channel devices according to the measurement results of ES / P (product of ENOB and sampling rate divided by power consumption) quality factor. Ltc1403 and ltc1403a have two low-power idling modes. In the nap mode, under normal power supply, the power consumption is reduced to the level of no more than 4.5mw. The chip keeps the internal reference voltage biased so that the converter can wake up in one clock cycle. In sleep mode, the bias of the reference is also turned off, and the power consumption is further reduced to a level not exceeding 45mA. Once in sleep, the converter takes 2 ms to wake up, mainly because of the benchmark conversion time and stabilization time, assuming that the load is the recommended 10mf.

When the frequency is lower than 100kHz, the CMRR (common mode rejection ratio) provided by the differential input of ltc1403a is generally higher than 80dB, exceeding the expected 20dB / 10x frequency roll off. The ENOB of the device is almost consistent with the characteristics of Nyquist. At this point, the ENOB will decrease as the distortion increases. A three wire serial control interface enables ltc1403 and ltc1403a to be placed in msop-10 package, making these devices very attractive for portable system or field embedded system applications.

Texas Instruments (TI) 12 bit ads7881 has a sampling speed of up to 4ms / s. Like the ltc1403, the ads7881 has two low-power standby modes, reducing the power consumption from the maximum of 110MW to less than 10MW in nap mode and 9 times in sleep mode μ W。 The recovery time is generally 60 ns and 25 ms respectively.

The sample / hold amplifier of ads7881 provides Pseudo differential input. You should drive this input with matched source impedance to minimize offset, gain and linearity error in the input voltage range and operating temperature range. The input signal range is 0 ~ 2.5V. “Pseudo” in pseudo difference means that the converter samples the input signals and sends them to the capacitor array, which suppresses the common mode components, but only within a limited voltage range of ± 200mV. In this range, the typical CMRR is equal to 60 dB at 1MHz.

Ads7881 has a parallel port, so it is packaged with tqfp-48. You can configure the 12 bit data port of the converter in byte mode for 8-bit processor. In this arrangement, your processor reads 12 bits of data during two consecutive byte reads.

Several applications such as I / Q demodulation and polyphase motor control benefit from synchronous sampling of signal pairs. The cheap dual channel converter meets this need by making efficient use of circuit board space and power supply. Linear technology’s 14 bit 1.5ms/s ltc1407a dual channel ADC provides simultaneous sampling on two sample / hold amplifiers, which share a 3MS / s SAR core (Figure 1). The converter switches back and forth between two sample / hold amplifiers and loads a pair of 14 bit latches.

Like the ltc1403a, the ltc1407a has a 12 bit sister product ltc1407, a power-saving nap mode and sleep mode, and a three wire digital interface, which is encapsulated in msop-10. The differential input range of this dual channel converter is 0 ~ 2.5V. The differential input can also accommodate the common mode signal as long as the sum of the differential component and the common mode component does not exceed the power supply voltage of the nominal value of 3V.

Analog devices ad7266 provides two complete 12 bit 2ms / s converters, which share a common reference and control block. Each converter has an input multiplexer, which you can configure for 3 differential input signals or 6 single ended input signals. You can choose to read two output words from two serial output pins or read them successively on a line.

The maximum power consumption of ad7266 is 20MW. It works on 5V power supply. According to our ES / P quality factor, it has become the SAR converter with the highest power efficiency in this survey. When using 3V power supply, the maximum conversion rate is reduced to 1.5ms/s, but the power consumption is reduced faster, and the maximum is only 8mW. The maximum power consumption of shutdown mode is 5MW.

The specification details of ad7266 have been incomplete since its launch, because it will not be fully produced until this year. Although SINAD, thd (total harmonic distortion) and SFDR (spurious free dynamic range) have maximum or minimum specifications, only typical values are given for the hard indicators you may want to know, such as crosstalk, jitter, bandwidth, offset matching, etc. The data table also lists other indicators such as maximum throughput as TBD (to be determined). The ad7266 is not the only device with a rough data sheet. The fact seems to be that when the largest and most active suppliers rush to put their latest and most competitive devices on the market, they do not leave enough details for early adopters. Analog devices is not the only company to make such a mistake. Its main rival, Texas Instruments, has been talking about its devices before providing complete specification details. This may be understandable in the first few weeks after the product launch, but there is still no news after two quarters, and people’s good appetite may have long gone.

Of course, analog devices and Ti are not just doing meaningless things. In case of exceeding 1ms / S (Table 2) Δ-Σ Converter (or Σ-Δ Converter, which depends on who you are talking to) in the field, they are in a leading position. During the last survey, such products did not exist. At that time, such devices were at best university papers. The first batch of samples are ads1605 and ads1606 of TI company and ad7400 and ad7401 of analog devices company.

Like the slower models in this type of converter, a digital filter is placed in Δ-Σ After the modulator, it determines many characteristics in the frequency band, including ± 0.0025db passband ripple, wide linear phase bandwidth, and sharp transition into the suppression band. The attenuation of the suppression band shall be at least 72db.

The data sheet specifies the minimum SINAD, and the full-scale input at 100kHz is – 20dB. If you use it to calculate ENOB, the results for ads1605 and ads1625 are 10 bits and 11.2 bits respectively. The estimated values in the table are obtained by combining SNR trend line and thd trend line. The ratio of minimum value to typical value at – 20dB full scale is rated. According to the characteristic curve of the data sheet, SNR and thd deteriorate sharply by more than 10dB in the last 2dB of the dynamic range. This strange characteristic makes it more difficult to evaluate the performance of these devices at other points other than 20dB full-scale point.

The ad7400 and ad7401 of analog devices are 16 bit 10ms / s self timing respectively Σ-Δ Converter and 16 bit 20ms / s external timing Σ-Δ converter. As of the time of writing, ad740x converters are very unusual in IC ADCs. Perhaps the unique thing is that they contain a planar insulated transformer, which enables you to eliminate the current isolation required in many AC motor control and data acquisition applications. The company’s isolation withstand test applied 4.5kv voltage to the device for 1s, and the leakage current limit was 5 μ A. According to ul1577 standard. The maximum allowable value of partial discharge test is 5pc, the voltage is 1.67kv, lasting for 1s, and it is carried out according to en60747-5-2 standard. These devices have been or are applying for approval in terms of UL, CSA, IEC, VDE, DIN and EN standards for isolation, insulation and working voltage.

Hot pipeline converter

The flash converter is the fastest converter architecture, limited by the fact that it requires an n-bit Precision Comparator for each code. Therefore, its area and final cost are proportional to 2n, where n is the number of bits. A circuit technology called folding reduces the number of comparators, but it is rare in converters with a resolution of more than about 8 bits (ref. 3). Adc-081000 of national semiconductor is a commercial converter using folding and interpolation architecture. It is a 1gs / s 8-bit device, which is intended to be used in digital oscilloscope, measuring instrument and direct RF down conversion equipment (reference 4). The company has only recently released this device, and the final performance limit has not been provided as of the time of publication. National semiconductor is scheduled to put the product into production and market soon. The price is US $100 (batch 1000 pieces).

Pipelined converters are the fastest common architectures for a variety of resolutions over 8 bits (Table 3). Whether from the perspective of commodity or academic experiment, pipelined converter has always been a major development topic. After more than about 12 bits, the pipelined converter design uses various calibration methods to eliminate the initial nonlinearity. This practice is particularly common when companies compete to manufacture faster, higher resolution converters with no corresponding increase in power consumption.

In terms of pipelined converters, the most noteworthy trends include increasing the sampling rate, increasing the ENOB of each sampling rate node, and providing more multi-channel devices. Multichannel converters are especially suitable for the fields of imaging and communication. In the field of imaging, large arrays are common, while in the field of communication, I / Q channels need well matched signal chains.

Texas Instruments took the lead in including multiple channels into the product. There are 8 channels in each package. These products are ads5270, ads5271 and ads5272, which are 12 bit converters of 40mms / s, 50mms / s and 65ms / s respectively. If the ENOB with a typical value of 11.3 bits did not cause much vibration when the company announced the minimum values, such channel density and low power consumption (less than 1W per package) should be very attractive for imaging applications such as portable ultrasonic equipment.

The converters of each channel are connected to a serializer and an LVDS driver. An external sampling clock synchronously drives eight sample / hold amplifiers and a PLL, which generates an output bit clock. Both sampling clock and bit clock are available at LVDS output.

Analog devices’ multi-channel pipelined converters include ad9229 12 bit converter and ad9289 8-bit converter. The working speed of both devices is 65ms / s, and both provide LVDS data output and bit clock output. Typical enobs are 11.4 bits and 7.5 bits, respectively. Similarly, as of the time of writing, the company has not provided limit specifications, so it is difficult to evaluate the overall performance of these devices.

Maxim max1126 and max1127 are 4-channel 40ms / s and 65ms / s pipelined converters respectively, which work with 1.8V power supply. Similar to other multi-channel converters, max1126 and max1127 share an on-chip reference, a clock buffer, a PLL and a control structure, so that the total power consumption does not exceed 2 / 3W. The differential input range of these converters is extended to 1.4V p-p. The minimum ENOB is 10.8 bits at 19.3mhz.

The noteworthy single channel pipelined converter includes 14 bit converter telasic tc1410, which has a working speed of 240ms / s, a bandwidth of 1GHz and an appropriate input matching network. The 14 bit ltc1750 of linear technology and the 15 bit max1427 of Maxim also deserve attention. The working speed of these two devices is 80ms / s and both provide 11.8 ENOB, but the resolution is different. The ltc1750 is 30 MHz and the max1427 is 15 MHz.

More new devices are also pipelined. Several manufacturers are planning to launch high-speed converters in the third and fourth quarters, so you can continue the “race to be first” game. With luck, for devices released in the past two quarters or earlier, they will also add specification details that were not provided at that time.

Attachment: single value paradox

The limited use of single value specifications for multiparameter phenomena will increase with some regularity in the simulation domain, and high-speed converters are no exception (reference a). Some OEM designers need components with guaranteed specifications and competitive prices, while the parameter tests done by some converter manufacturers who are eager to support customers have accounted for a large part of the total ex factory cost of IC. For these designers and manufacturers, this problem is somewhat contradictory. For example, clock rate, input frequency and operating temperature are three parameters that affect the performance of the converter. From this point of view, although the single valued ENOB (effective bit number) specification is simple and attractive, it is unlikely to contain as much information as you want unless the standards that limit signals and operating conditions strongly guide your application.

Chip manufacturers have long used characteristic curves to supplement their specification sheets, which usually represent from one-off α Test the statistical average of the data collected. Continuous process monitoring and yield optimization often place key parameters in the center and are accompanied by well controlled distribution, so the effective life of these data exceeds the wafer on which they are based. In addition, some manufacturers provide parameter distribution histograms that help depict the relationship between typical performance and the maximum and minimum values of the specification table. When interpreting characteristic curves for multi parameter measures, one difficulty is that they only provide two-dimensional fragments of device performance, so you have to estimate the corner size in the dimension of three or more parameters.

For high-speed ADC, the least intuitive relationships include noise characteristics, distortion characteristics and parasitic characteristics, which are functions of clock rate and input frequency. Therefore, it is noteworthy to look for manufacturers who try to clarify these complex relationships with graphics. Texas Instruments does this in the data table of ads5500 converter (14 bits, 125ms / s) (figure a).

Figure a shows the functional relationship between SNR (a), parasitic free dynamic range (b), second harmonic distortion and sampling rate and input frequency of ads5500 of TI company, showing the complex relationship between converter performance and signal transmission conditions.

Responsible editor: GT

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