Author: Pablo Perez, Jr., Senior Application Engineer of ADI company John Martin dela Cruz, application engineer

brief introduction

Part 1 of this series on signal chain power optimization discusses how to quantify power supply noise to determine which parameters it affects signal chain devices. An optimized distribution network (PDN) can be created by determining the actual noise limit that the signal processing device can accept without affecting the integrity of the signal it generates. In the second part, this method is applied to high-speed analog-to-digital and digital to analog converters. It is proved that reducing the noise to the necessary level does not necessarily improve the cost, increase the size and reduce the efficiency. These design parameters can actually be met in an optimized power solution.

This paper focuses on another part of the signal chain – RF transceiver. This paper will explore the sensitivity of devices to noise from each power rail and determine which devices need additional noise filtering. This paper provides an optimized power supply solution, which is further verified by comparing its SFDR and phase noise performance with the current PDN (when connected to RF transceiver).

Optimize the power system of adrv9009 6 GHz dual channel RF transceiver

Adrv9009 is a highly integrated radio frequency (RF) and agile transceiver, which provides dual channel transmitter and receiver, integrated frequency synthesizer and digital signal processing functions. This IC has a diversified combination of high performance and low power consumption, which can meet the requirements of 3G, 4G and 5g macro cellular time division duplex (TDD) base station applications.

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Figure 1 Adrv9009 dual channel transceiver standard evaluation board distribution network. This setting uses an adp5054 four channel regulator and four LDO post regulators to meet the noise specifications and maximize the performance of the transceiver. The goal is to improve the solution.

Figure 1 shows the standard PDN of the adrv9009 dual channel transceiver. PDN consists of an adp5054 four channel switching regulator and four linear regulators. The goal here is to understand which performance parameters of the distribution network can be improved, and the generated noise will not reduce the performance of the transceiver.

As described in this series of articles, 1,2, in order to optimize PDN, it is necessary to quantify the sensitivity of adrv9009 to power supply noise. The adrv9009 6 GHz dual channel RF transceiver requires the following five different power rails:

  • 1.3 V analog (vdda1p3_an)
  • 1.3 V digital (vddd1p3_dig)
  • 1.8 V transmitter and BB (vdda_1p8)
  • 2.5 V interface (vdd_interface)
  • 3.3 V auxiliary (vdda#u 3p3)

analysis

Figure 2 shows the receiver 1 Port psmr results of the analog power rails (vdda1p3_an, vdda_1p8, and vdda_3p3). For digital power rails (vddd1p3_dig and vdd_interface), the maximum injection ripple that can be generated by the signal generator does not generate spurious in the output spectrum, so we do not need to worry about minimizing the ripple on these power rails. The modulation spurious amplitude is expressed in dBfs, where the maximum output power (0 DBF) is equivalent to 7 DBM or 1415.89 MV P-P in a 50 Ω system.

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Figure 2 Psmr performance of analog power rail of adrv9009 transceiver at receiver 1

For vdda1p3_ For an power rail, the measurement is carried out on two different branches of the transceiver board. Note that in Figure 2, psmr is lower than 0 dB at 200kHz ripple frequency, indicating that the ripple at these frequencies produces higher modulation spurious of the same amplitude. This means that below 200 kHz, receiver 1 is also very sensitive to the minimum ripple generated by vdda1p3_an power rail.

VDDA_ The 1p8 power rail is divided into two branches on the transceiver board: vdda1p8_ TX and vdda1p8_ BB。 VDDA1P8_ The TX power rail reaches a minimum psmr of about 27 dB at 100 kHz, corresponding to 63.25 MV P-P of 100 kHz ripple, resulting in 2.77 MV P-P modulation spurious. VDDA1P8_ BB measures a minimum of about 11 dB at a ripple frequency of 5 MHz, equivalent to 0.038 MV P-P spurious generated by an injection ripple of 0.136 MV p-p.

VDDA_ 3p3 data shows that the psmr is less than 0 dB at about 130 kHz and below, indicating that the RF signal at receiver 1 is from vdda_ 3p3 is very sensitive to noise. The psmr of the power rail rises with the increase of frequency and reaches 72.5 dB at 5 MHz.

In conclusion, psmr results show that in these power rails, vdda1p3_ An and vdda_ 3p3 power rail noise is the most worrying, contributing to the ripple amount of the largest part of the adrv9009 transceiver coupled to receiver 1.

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Figure 3 PSRR performance of analog power rail of adrv9009 transceiver at receiver 1

Figure 3 shows the PSRR performance of the adrv9009 analog power rail. VDDA1P3_ The PSRR of an remains flat at the highest 1MHz, about 60 db; It drops slightly at 5 MHz, with a minimum of 46 dB. This can be considered as a 0.127 MV P-P ripple of 5 MHz, which produces a 0.001 MV P-P spurious which, together with the modulated RF signal, is above the LO frequency.

Vdda1p8 of adrv9009_ The PSRR of BB power rail reaches a minimum value of about 47 dB at 5 MHz, while vdda1p8_ The PSRR of TX power rail will not be less than about 80 dB. In the spectrum below 1 MHz, vdda_ The PSRR of 3p3 is higher than 90 dB shown. The measurement is clipped at 90 dB because the maximum injection ripple of up to 1 MHz is 20 mV P-P – which is not high enough to produce spurious noise above the background noise of the local oscillator. The PSRR of the power rail is higher than the case below 1 MHz shown, because as the frequency increases, it decreases to 76.8 dB at 4 MHz, and its minimum value is in the range of 10 kHz to 10 MHz.

Similar to psmr results, PSRR data show that most of the noise coupled to the local oscillator frequency (especially higher than 1 MHz) comes from vdda1p3_ An and vdda_ 3p3 power rail.

In order to determine whether the power supply can meet the noise requirements, measure the ripple output of the DC power supply and draw a waveform in the frequency range of 100 Hz to 100 MHz, as shown in Figure 4. A covering layer is added to the spectrum: the threshold of sideband spurious will appear in the modulated signal. The covered data is obtained by injecting sinusoidal ripple into the specified power rail at several reference points to understand what ripple level produces sideband spurious, as discussed in part 1 of this series.

The threshold data shown in FIGS. 4 to 6 are for the three power rails most sensitive to the transceiver. The figure shows the power rail spectrum under different DC-DC converter configurations, enabled / disabled spread spectrum (SSFM), more filtering through LDO regulator or low-pass (LC) filter, etc. These waveforms are measured on the power board and leave a margin of 6 dB or more lower than the noise limit.

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Figure 4 Vdda1p3_ Output noise spectrum of ltm8063 (different configurations) powered by an power rail,

And the maximum ripple allowed by the power rail.

test

Figure 4 shows vdda1p3_ Stray threshold of an power rail and ltm8063 µ module ® Measured noise spectrum of different configurations of voltage regulator. As shown in Figure 4, when spread spectrum (SSFM) is disabled, ltm8063 is used to directly supply power to the power rail, and a ripple exceeding the threshold is generated at the fundamental operating frequency and harmonic frequency of ltm8063. Specifically, the ripple exceeds the limit value of 0.57 MV at 1.1 MHz, indicating that some combination of post regulator and filter is required to suppress the noise of switching regulator.

If only LC filter is added (without LDO regulator), the ripple at the switching frequency just reaches the maximum allowable ripple – there may not be enough design margin to ensure optimal transceiver performance. Adding adp1764 LDO post regulator and turning on the spread spectrum mode of ltm8063 can reduce the fundamental switching ripple amplitude and its harmonics in the whole spectrum, as well as the noise peak caused by SSFM in the 1 / F region. By turning on SSFM and adding LDO regulator and LC filter, the best effect can be achieved, the residual noise caused by switching action can be reduced, and about 18 dB margin is left for the maximum allowable ripple.

Spread spectrum spreads the noise over a wider frequency band, thereby reducing the peak and average noise at the switching frequency and its harmonics. This is achieved by modulating the switching frequency up and down with a 3 kHz triangular wave. This will introduce a new ripple at 3 kHz and the LDO regulator will process it.

After enabling SSFM, the resulting low-frequency ripple and its harmonics are in the vdda shown in figures 5 and 6_ 1p8 and vdda_ It is obvious in the 3p3 output spectrum. As shown in Figure 5, when SSFM is enabled, the noise spectrum of ltm8074 is vdda_ The maximum allowable ripple of 1p8 power rail provides a minimum margin of about 8 dB. Therefore, post regulator filtering is not required to meet the noise requirements of this power rail.

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Figure 5 For vdda_ The output noise spectrum of ltm8074 (SSFM on) powered by 1p8 power rail and the maximum ripple allowed by the power rail.

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Figure 6 For vdda_ The output noise spectrum of ltm8074 (different configurations) powered by 3p3 power rail and the maximum ripple allowed by the power rail.

Note the sensitivity of the power rail to low-frequency ripple, as this noise may cause phase jitter in a 3.3 V powered clock.

Figure 6 shows the ltm8074 μ Noise spectrum of different configurations of module regulator and 3.3V vdda_ Maximum noise requirements of 3p3 power rail. For this power rail, we use the ltm8074 silent switch ® μ Module voltage regulator to analyze the results. The noise generated by using only the configuration of ltm8074 (no filter or LDO post regulator) exceeds the limit, regardless of whether the spread spectrum mode is enabled or not.

The results of two alternative configurations meet the noise specification of 6 dB margin: ltm8074 with LC filter without SSFM enabled and ltm8074 with LDO post regulator with SSFM enabled. Although both meet the requirements with sufficient margin, LDO post regulator solution has more advantages here. This is because vdda_ The 3p3 power rail also provides 3p3v_ CLK1 clock power supply, so the reduction of 1 / f noise is relatively more important – if not processed, the noise here can be converted into phase jitter in the local oscillator.

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Figure 7 Use ltm8063 and ltm8074 μ Adrv9009 transceiver optimization PDN of module regulator

Optimization solution

Based on the above test results, Figure 7 shows an optimized solution, which can provide a 6 dB noise margin when used on the adrv9009 transceiver board.

Table 1 shows the comparison between optimized PDN and standard PDN. The component size is reduced by 29.8%, the efficiency is increased from 66.9% to 69.9%, and the overall energy saving is 0.5 W.

Table 1 Comparison between adrv9009 optimized PDN and current PDN

In order to verify the effect of the optimized power solution on the system noise performance, we performed phase noise measurement. Compare the optimization solution in Figure 7 with the control case, the engineering version of the adrv9009 evaluation board, that is, the ad9378 evaluation board using the PDN shown in Figure 1. Using the same circuit board, but using the PDN shown in Fig. 7, compare the phase noise results. Ideally, the optimized solution achieves or exceeds the performance shown in the data book reference curve.

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Figure 8 Comparison of ad9378 phase noise performance between adp5054 and PSU of µ module device,

Measurement conditions: lo = 1900 MHz, PLL BW = 425 kHz, stability = 8.

Figure 8 compares the phase noise results of the ad9378 evaluation board using the standard adp5054 power supply with the results of the same evaluation board using the ltm8063 and ltm8074 power supplies. Compared with adp5054 power solution, μ The performance of the module power solution is slightly better, about 2 dB higher. As shown in Figure 8 and table 2, since the external Lo uses a low phase noise signal generator, the measurement results of both power solutions are significantly lower than the specifications of the data book.

Table 2 Phase noise measurement, Lo = 1900 MHz

The SFDR measurement results of transceivers with two power supply solutions are shown in Table 3. The performance of the two solutions is equivalent, except that Lo = 3800 MHz. In this case, the switching ripple of adp5054 begins to generate modulation spurious on the output spectrum of carrier signal, as shown in Figure 9.

Table 3 Adrv9009 transceiver SFDR performance

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Figure 9 The spurious frequency caused by the carrier signal of transmitter 1 and the switching frequency of power supply.

Measurement conditions: lo = 3800 MHz, FBB = 7 MHz, – 10 DBM.

conclusion

Different applications have different requirements, and the distribution network of the evaluation board may need to be further improved or changed. The ability to quantify signal processing IC noise requirements provides a more effective way to power design or simply optimize existing power solutions. For high-performance RF transceivers such as adrv9009, setting noise injection in PDN to determine that it can accommodate many large power supply noise helps us to improve the space requirements, efficiency and critical thermal performance of current PDN. Please continue to pay attention to the subsequent articles of this power system optimization series.

Introduction to the author

Pablo Perez, Jr. joined ADI in May 2019 as ADEF Senior Application Engineer. His work experience includes modifying and evaluating standard switching mode power supplies in different application fields (industrial, telecommunications, medical, military), as well as design verification and sample evaluation of linear regulator, switching regulator and power management IC. Pablo graduated from Manuel s. everga university foundation, Inc., Lucena, Quezon Province, Philippines, with a bachelor’s degree in electronic and communication engineering.

John Martin dela Cruz joined ADI in October 2020 as a power application engineer. He is mainly responsible for aerospace and defense (ADEF) power systems. He graduated from the University of the Philippines (diriman, Quezon, Philippines) with a bachelor’s degree in electronic engineering.

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