Integrating multiple digital signal processing (DSP) modules, broadband digital to analog converter (DAC) and broadband analog-to-digital converter (ADC) into a single chip, the power consuming FPGA resources can now be unloaded to a platform that allows smaller size, lower power consumption and increase the number of channels, and can sample at a higher rate than before. In addition to this new feature, these integrated circuits (ICS) are equipped with novel multi chip synchronization (MCS) algorithms that allow users to achieve known (deterministic) phases for all channels when powering the system or otherwise modifying the system software. Therefore, this deterministic phase simplifies a wider range of system level calibration algorithms that need to synchronize all channels at the output or input of the front-end network connected to these ICs. This paper introduces the experimental results of demonstrating this MCS capability when using a 16 channel receiver / transmitter platform composed of multiple digitizer ICs, clock sources and digital interfaces.
Advanced system block diagram
The system block diagram for this test is shown in Figure 1. It is composed of four integrated DAC / ADC / DSP ICs. Each IC is composed of four 12 GSPS DAC, four 4 GSPS ADC, 12 digital up converter (Duc) and 12 digital down converter (DDC) blocks.
Figure 1 High level system block diagram for demonstrating MCS and multi-channel calibration algorithm. (source: ADI)
Duc / DDC allows frequency conversion and / or interpolation / decimation in the digital domain. Use a single 500 MHz reference clock on the injection board, and then use the reference lock clock buffer to generate the system reference signal required by the MCS and the clock required for the digital interface with the baseband processor (BBP). The system also includes four independent phase locked loop (PLL) synthesizers that generate the required 12 GHz signal source to provide a clock for each digital IC from a common reference. An RF front end is connected to each digitizer output / input, which creates a filtered and amplified signal to / from the RF connector transmitted by the edge. A complete power distribution solution is realized. All voltages required by the system are generated by a single 12 V power supply.
Subarray clock tree structure
As mentioned earlier, the subarray clock tree consists of a single 500 MHz reference source, which is split and sent to the reference inputs of four independent PLL synthesizer ICs, as shown in Figure 1 above. This 500 MHz signal is also 10 dB coupled, amplified and sent to another clock buffer IC, which is responsible for generating the system reference (sysref) and BBP clock required for the digital interface. The goal of this clock tree is threefold because it:
Allow a single channel sysref delay to correct any routing length mismatch between ICs.
Separate PLL / synthesizer phase adjustments are allowed, thus ensuring synchronization between the various digitizer IC clock sources to compensate for any induced thermal gradients in the system.
Enable users to realize the necessary setting and maintenance requirements of Digital IC.
The clock tree IC is selected to prove that various board layout abnormalities can be corrected in software and / or hardware with the help of digital and analog delay blocks existing in these chips. The final result is a clock tree, which can provide sysref pulses to all required ICs in the same sampling clock cycle of each IC.
Digital interface with baseband processor
Each of the four digital ICs establishes a jesd204b or jesd204c digital link interface with BBP. 1,2 this interface is responsible for transmitting ADC and DAC codes to and from BBP through physical routing (SerDes). The number of differential SerDes traces used in this interface is called the number of channels (L) of this link. The bit resolution of the converter transmitted over the link is regarded as n ‘. The number of channelized data paths (also known as virtual converters) is marked M. The results shown in this paper use jesd204c link, where M = 16, n ‘= 16, l = 4 are used for DAC side link, M = 8, n’ = 16, l = 2 are used for ADC side link.
The rate at which data is transmitted and received between the digitizer IC and the BBP is called the channel rate. The DSP module (DDC / Duc) on the silicon chip allows the user to sample the digitizer at a rate different from the data rate sent through the physical channel. Therefore, the channel rate depends on the digital extraction / interpolation data rate of each data path. For this work, a 250 MSPs I / Q data rate is used. For the jesd204c interface, the channel rate is defined as:
For the jesd204b interface, the channel rate is defined as:
The results shown in this paper use a channel rate of 16.5 Gbps for both ADC and DAC jesd204c links.
Each jesd204b / jesd204c link can be established in different subclasses. These subclasses are separated according to whether multi chip synchronization or deterministic delay is required. For this work, the displayed data uses the jesd204c subclass 1 mode, so the sysref signal is used to align some digital data transmitted through multiple links existing in the system. Specifically, in this jesd204c subclass 1 mode, the sysref signal is used to align the local extended multi block counter (lemc), and its transmission rate is:
Where f is the number of octets of each jesd frame of each channel, and K is the number of frames of each single multi frame. For this work, f = 8 and K = 32, so the lemc rate of 7.8125 MSPs is used. Understanding this lemc rate is important because any successful MCS routine needs to prove that RF frequencies that are not integral multiples of the lemc rate can achieve a deterministic power on phase.
Multi chip synchronization mode
In this system, the broadband integrated ADC / DAC IC provides MCS circuits to allow power on deterministic phase on all transmit and receive RF channels, even when using the Duc / DDC DSP module in the IC. This MCS function enables the user to populate the lookup table (LUT) during factory calibration to minimize operational downtime. Any successful MCS demonstration must be able to provide deterministic phases of all channels in the system for each attempted RF frequency, thermal gradient and system power cycle.
The integrated ADC / DAC IC includes 12 Duc modules and 12 DDC modules, as shown in Figure 1 above. Each of these modules contains an interpolation (Duc) or decimation (DDC) sub module, which is used to change the data rate of DAC digital input signal or ADC to digitize the output signal respectively. Each Duc / DDC also contains a complex numerical control oscillator (NCO), which allows frequency conversion in the digital domain. Each of these NCOs can perform real-time complex phase adjustment so that the digital signal between DAC / ADC and BBP can be modified to compensate for various SerDes routing length mismatches.
The MCS functions of these ADC / DAC ICs are responsible for achieving phase certainty in all aspects of the digitizer IC data path. The workflow of MCS is shown in Figure 2.
Figure 2 The MCS workflow involves separate functions that align different parts of the data path. (source: ADI)
MCS algorithm can be divided into two independent functions:
One time synchronization: this function is responsible for aligning the baseband data sent through the physical channels of all digitizer ICs in the sub array system.
NCO master-slave synchronization: this function is responsible for aligning all NCOs in all different digitizer ICs in the subarray system.
The one-time synchronization function first requires the user to define jesd link parameters (e.g. m, n ‘, l, etc.), and then configure the synchronization logic for any required sysref average (if continuous sysref pulses are used). In addition, the required lemc delay can be used to force lemc generation at a delay after the sysref edge. After completing this operation, the user then enables the one-time synchronization bit in each digitizer IC, and then requests that the sysref pulse be sent to each IC in the same clock cycle, as shown in Figure 3.
Figure 3 MCS algorithm uses sysref signal to realize one shot synchronization and GPIO signal to realize NCO master-slave synchronization to realize deterministic phase. (source: ADI)
For this system, an analog fine delay is introduced into the clock buffer IC to allow synchronization of sysref to all digitizer ICs. Subsequent checks can be performed by querying the registers in each IC to verify the successful execution of the one-time synchronization process. These registers provide information about the phase relationship between the sysref signal and the lemc boundary of each IC link.
Once the stable phase is measured (i.e. once the sysref-lemc phase register reads 0), the user will know that the lemcs of all digitizer ICs have been aligned, and then the user can continue the NCO master-slave synchronization process. For this activity, the subtasks described for one-time synchronization are included in the application programming interface (API) provided by the chip manufacturer.
NCO master-slave synchronization function first designates a digitizer IC in the sub array as the master chip, as shown in Figure 3. All other digitizers are then considered slave ICs. The setting of the master IC enables the gpio0 pin of the device to be configured as output and routed to the gpio0 network of three slave digitizer ICs. Configure from gpio0 network as input. Then, the user can choose to trigger at sysref pulse, lemc rising edge or lemc falling edge. For the data shown in this paper, lemc is used as NCO master-slave synchronization trigger source, and GPIO network is routed through BBP instead of local routing on sub array. Next, switch the DDC synchronization bit to low level and then to high level to start the NCO synchronization algorithm at the ADC end. similarly,
When this trigger is requested, at the rising edge of the next lemc, the main digitizer IC sets the main output signal to high level through its gpio0 network. The signal propagates to the gpio0 input of each slave device. At the next lemc edge, all digitizer ICs will undergo NCO reset algorithm. Thereafter, for NCO master-slave synchronization algorithm, any lemc pulse will be ignored. Like one-time synchronization, these NCO master-slave synchronization subtasks are included in API functions for user convenience.
Using the one-time synchronization and NCO master-slave synchronization functions, the two inputs can be aligned with each DDC / Duc, so that the output phase offset of each receiving and transmitting channel can be repeated after multiple power cycles, as shown in Figure 4. Figure 4 shows the calibration phase offset of each receive and transmit channel over 100 power cycles (represented by multiple solid points) when the system operates under a static thermal gradient during each restart.
Figure 4 When the MCS algorithm is executed, the receiving fine DDC (left) and transmitting fine Duc (right) are aligned correctly. (source: ADI)
From the multiple points in the figure, it can be seen that the points of each color of a given DDC / Duc are closely clustered in the same position after the power cycle, thus depicting the deterministic stage of the specific channel. For the data in this test, all eight Channeler DUCS have been used at the transmitter, while only four of the eight Channeler DDCS have been used. However, it has been confirmed that all eight Channeler DDCS provide deterministic phase while using MCS algorithm.
If the PLL synthesizer sampling clock and Clock IC sysref maintain the same phase relationship at startup, issuing this algorithm at startup will establish a deterministic phase for each channel. However, any system will experience thermal gradient, which will lead to PLL clock drift. If it is not compensated, it may lead to different power on stages. In order to compensate the thermal gradient drift in the system, the platform uses PLL synthesizer phase adjustment.
In the next part of this series, we will explore PLL synthesizer phase adjustment, scalability of multiple subarrays, and system level calibration algorithms.
1 del Jones. “Getting started with jesd204c: what’s new and what’s right for you – Part 1.” Simulation dialog, volume. 53, No. 2, June 2019.
2 del Jones. “Getting started with jesd204c: what’s new and what’s right for you – Part 2.” Simulation dialog, volume. 53, No. 3, July 2019.
Mike Jones is the Chief Electrical Design Engineer of ADI and works in the aerospace and defense business department in Greensboro, North Carolina. He joined ADI in 2016. From 2007 to 2016, he worked at General Electric in Wilmington, North Carolina as a microwave photonic design engineer, focusing on microwave and optical solutions for the nuclear industry. He received BSEE and bspe from North Carolina State University in 2004 and MSEE from North Carolina State University in 2006.
Michael hennerich joined ADI in 2004. As a system and application design engineer, he is engaged in various applications and reference designs based on DSP / FPGA and embedded processors. Michael now works as an open source systems engineering manager at the system development group (SDG) in Munich, Germany. In this position, he leads ADI’s device driver and kernel development team to develop device drivers for various mixed signal IC products and HDL interface cores. He has a master’s degree. Degree in Computer Engineering and Dipl- Ing。 (FH) degree in electronics and information technology from roetlingen University.
Peter Delos is the technical director of ADI’s aerospace and defense division in Greensboro, North Carolina. He received a bachelor’s degree in electrical engineering from Virginia Tech University in 1990 and a master’s degree in electrical engineering from the New Jersey Institute of technology in 2004. Peter has more than 25 years of industry experience. He spent most of his career designing advanced RF / analog systems at architecture level, PWB level and IC level. He is currently focused on miniaturizing the design of high-performance receivers, waveform generators and Synthesizers for phased array applications.