Analog to digital conversion is the technology of converting analog input signal into n-bit binary digital output signal. Using digital signal processing can easily realize various advanced adaptive algorithms and complete the functions that can not be realized by analog circuits. Therefore, more and more analog signal processing is being replaced by digital technology. Accordingly, as a bridge between analog system and digital system, analog-to-digital conversion is increasingly widely used. In order to meet the needs of the market, chip manufacturing companies continue to introduce more advanced new products and technologies. This paper analyzes and compares several most commonly used analog-to-digital conversion technologies.
1 Analog to digital conversion technology
Analog to digital conversion includes four processes: sampling, holding, quantization and programming. Sampling is to convert a continuously changing signal x (T) into a discrete sampling signal x (n) in time. According to Nyquist sampling theorem, for the sampled signal x (T), if the sampling frequency FS is greater than or equal to 2fmax (Fmax is the highest frequency component of X (T), the original signal x (T) can be reconstructed and restored without distortion. In fact, due to the nonlinear distortion of analog-to-digital converter devices, quantization noise and receiver noise, the sampling rate is generally FS = 2.5fmax. Generally, the width TW of the sampling pulse is very short, so the sampling output is an intermittent narrow pulse. To digitize a sampled output signal, the instantaneous analog signal obtained from the sampled output needs to be held for a period of time, which is the holding process. Quantization is to convert the continuous amplitude sampling signal into discrete-time and discrete amplitude digital signal. The main problem of quantization is quantization error. Assuming that the noise signal is evenly distributed in the quantization level, the mean square value of the quantization noise is related to the quantization interval and the input impedance value of the analog-to-digital converter. Coding is to encode the quantized signal into binary code for output. Some of these processes are combined. For example, sampling and holding are completed continuously by one circuit, quantization and coding are realized simultaneously in the conversion process, and the time used is part of the holding time. There are many technologies to realize these processes, from the integral type as early as the 1970s to the latest pipelined analog-to-digital conversion technology. Due to different principles, their performance characteristics are different.
1.1 integral analog-to-digital converter
Integral analog-to-digital converter, called double slope or multi slope data converter, is the most widely used type of converter. The typical is the double slope converter. We take it as an example to illustrate the working principle of the integral analog-to-digital converter. The dual slope converter consists of two main parts: one part of the circuit samples and quantizes the input voltage to generate a time domain interval or pulse sequence, which is then converted into digital output by a counter, as shown in Figure 1.
The dual slope converter is composed of an analog integrator with input switching switch, a comparator and a counting unit. The integrator integrates the input voltage within a fixed time interval, which usually corresponds to the maximum number of internal counting units. When the time arrives, reset the counter and connect the integrator input to the negative reference voltage. Under the action of this reverse polarity signal, the integrator is “reverse integrated” until the output returns to zero, terminates the counter and resets the integrator.
The sampling speed and bandwidth of integral analog-to-digital converters are very low, but their accuracy can be very high, and their ability to suppress high-frequency noise and fixed low-frequency interference (such as 50Hz or 60Hz) makes them useful for noisy industrial environment and applications that do not require high conversion rate (such as quantization of thermocouple output).
1.2 successive approximation ADC
The successive approximation converter includes a comparator, a digital to analog converter, a successive approximation register (SAR) and a logic control unit, as shown in Fig. 2. The successive approximation in the conversion is completed by the control logic circuit according to the bisection principle. The general process is as follows: after starting the conversion, the control logic circuit first approximates the highest position 1 and other positions 0 of the register step by step, and obtains the voltage value about half of the full-scale output after digital to analog conversion. This voltage value is compared with the input signal in the comparator. The output of the comparator is fed back to the digital to analog converter and corrected before the next comparison. Driven by the clock of the logic control circuit, the successive approximation register continues to compare and shift until the conversion of the least significant bit (LSB) is completed. At this time, each value of the successive approximation register has been determined, and the successive approximation conversion is completed.
Because the successive approximation analog-to-digital converter can only complete 1-bit conversion in one clock cycle. N-bit conversion requires n clock cycles, so the sampling rate of this analog-to-digital converter is not high and the input bandwidth is low. It has the advantages of simple principle, easy implementation and no delay problem. It is suitable for occasions with medium speed and high resolution requirements.
1.3 scintillation ADC
Compared with the general analog-to-digital converter, the scintillation analog-to-digital converter is the fastest. Because there is no need for successive comparison, it does not convert n-bit data n times, but only once, so the speed is greatly improved. Fig. 3 shows the principle of n-bit scintillation analog-to-digital converter. There is a certain reference voltage in the converter, and the analog input signal is added to 2N-1 latch comparators at the same time. The reference voltage of each comparator is led out by a voltage divider composed of a resistance network, and its reference voltage is one least significant bit higher than the reference voltage of the next comparator. When the analog signal is input, those comparators whose wind reference voltage is lower than the analog signal output a high level (logic 1), and vice versa output a low level (logic 0). The number thus obtained is called thermometer code. The code is added to the decoding logic circuit and then sent to the output register on the binary data output driver.
Although the scintillation converter has extremely fast speed (up to 1GHz sampling rate), its resolution is limited by the die size, excessive input capacitance and power consumption caused by a large number of comparators. Precise matching is also required between parallel comparators with repeated structure, so any mismatch will cause static error, such as increasing the input offset voltage (or current).
Scintillation ADC is also easy to produce discrete and uncertain output, that is, the so-called “scintillation code”. There are two main sources of scintillation Code: metastable state of 2N-1 comparator and thermometer coded bubble; A mismatched comparator delay changes logic 1 to logic 0 (or vice versa), as if a bubble appeared in the thermometer. Since the encoding unit in the analog-to-digital converter cannot recognize this error, the encoded output will also “flicker”.
Another consideration for scintillation ADC is die size. An 8-bit scintillation converter is nearly 7 times larger than a pipelined analog-to-digital converter with the same number of bits. Compared with the pipelined structure, the input capacitance and power consumption of the scintillation converter are 6 times and 2 times higher, respectively.
1.4 ∑- Δ Type A / D converter
∑- Δ The converter is also called oversampling converter. This converter consists of sigma- Δ The modulator is composed of a digital filter connected with it, as shown in Fig. 4. The structure of the modulator is similar to that of a double slope analog-to-digital converter, including an integrator, a comparator and a feedback loop containing a 1-bit analog-to-digital converter. The built-in digital to analog converter is just a switch that switches the integrator input
Change to a positive or negative reference voltage. ∑- Δ The analog-to-digital converter also includes a clock unit to provide appropriate timing for modulation and digital filters. Narrowband signal into Σ- Δ The analog-to-digital converter is quantized at a very low resolution (1 bit), but the sampling frequency is very high. After digital filtering, the oversampling is reduced to a relatively low sampling rate; At the same time, the resolution (i.e. dynamic range) of the analog-to-digital converter is improved to 16 bits or higher.
Although Σ- Δ The sampling rate of analog-to-digital converter is low and limited to narrow input bandwidth, but it still occupies a very important position in the analog-to-digital converter market. It has three main advantages:
*Low price, high performance (high resolution);
*Integrated digital filtering;
*Compatible with DSP technology and easy to realize system integration.
2 pipelined ADC
From the above introduction of several common analog-to-digital converters, it is not difficult to see that they all have some shortcomings, and the pipelined (or sub area) analog-to-digital converter is a more efficient and powerful analog-to-digital converter. It can provide high-speed, high-resolution analog-to-digital conversion, and has satisfactory low power consumption and small chip size (meaning low price); After reasonable design, it can also provide excellent dynamic characteristics.
The functional block diagram of pipelined analog-to-digital converter is shown in Figure 5. The analog-to-digital converter with this structure uses multiple low-precision scintillation analog-to-digital converter sampling signals for hierarchical quantization, and then combines the quantization results at all levels to form a high-precision quantization output. Each stage is composed of a sample / hold circuit (T / h), a low resolution analog-to-digital converter, a digital to analog converter and a summation circuit. The summation circuit also includes an interstage amplifier that can provide gain. The procedure for a n-bit resolution pipelined analog-to-digital converter to complete one sampling is roughly as follows:
After the input signal of the sampling / holding device of the primary circuit is sampled, the input is quantized by a coarse analog-to-digital converter with m-bit resolution, and then an analog level corresponding to the quantization result is generated by a product digital to analog converter (MDAC) with at least n-bit accuracy and sent to the summation circuit. The summation circuit subtracts the analog level from the input signal, accurately amplifies the difference to a fixed gain, and then sends it to the next stage circuit for processing. After L-level processing, the residual signal is finally converted by a high-precision k-bit fine analog-to-digital converter. The outputs of coarse and fine a modules at all levels are combined to form a high-precision n-bit output. In order to correct the overlap error, redundant bits are reserved for circuits at all levels of the pipeline, that is to meet the following requirements:
L × M+K＞N
Where l is the number of stages (different manufacturers), and M is the coarse resolution of analog-to-digital converter circuit in each stage. K is the fine resolution of the fine analog-to-digital converter stage, and N is the total resolution of the pipelined analog-to-digital converter.
In pipelined analog-to-digital converter, each circuit has its own tracking / holding circuit. Therefore, when the signal is transmitted to the secondary circuit, the tracking / holding device of the current circuit can be released to process the next sampling. In this way, the throughput of the whole circuit is improved, and one sampling can be completed in one clock cycle. In order to compensate for undesirable boundary effects, such as temperature drift or capacitor mismatch in product digital to analog converters, some pipelined module converters are also equipped with correction units. This unit is usually used in multi-stage (not all) circuits of pipeline. Two correction codes are used to make the output amplitude of product digital to analog converter equal to the jump of VREF, and any deviation from this jump will be measured. The errors of converters at all levels are collected and stored in the internal memory. During normal operation, the results are retrieved from RAM and compensated for the gain of each link of the water line and the capacitance mismatch of the product digital to analog converter.
In short, the pipeline structure simplifies the design of analog-to-digital converter and has the following advantages:
*The redundant bits of each line optimize the correction of overlap error;
*Each stage has its own independent sample / hold amplifier, and the sample / hold of the previous stage circuit can be released for processing the next sampling, so it is allowed to process multiple samples at each stage of the pipeline at the same time;
*Lower power consumption;
*Higher sampling speed, lower price, less design time and less difficulty;
*Few comparators enter metastable state, which fundamentally eliminates the bubble of scintillation code thermometer.
But at the same time, pipelined analog-to-digital converter also has some disadvantages:
*Complex reference circuit and bias structure;
*The input signal must pass through several stages of circuit, resulting in water delay;
*Strict latch timing is required to synchronize all outputs;
*It is sensitive to process blanking, which will affect gain nonlinearity, misalignment and other parameters;
*Compared with other conversion technologies, it is more sensitive to printed board wiring.
However, the reasonable design of multilayer printed board line can overcome many of the above disadvantages. The selection of external components and the selection of appropriate models of pipelined analog-to-digital converter (preferably including internal inter stage gain and error mismatch calibration) can also improve the performance of the system.
With the rapid development of analog-to-digital conversion technology, pipelined analog-to-digital conversion technology is only one of them. I believe that with the rapid development of digital technology and microelectronics technology, newer and better analog-to-digital conversion technology will appear. Finally, I hope this paper can provide some reference for readers when choosing suitable analog-to-digital converter.
Responsible editor: GT