Ad9755 is a 14 bit analog-to-digital conversion chip with ultra-high speed double ended data multiplexing and single output produced by analog device. Using CMOS manufacturing process, high-quality 14 txdac + (R) core, a reference voltage source, compatible TTL digital interface circuit unit and ppl clock converter are integrated on a single chip. Its conversion speed is very high and can reach 300 ms / s.

The chip has less demand for peripheral circuits and is flexible and convenient to design and use. Ad9755 provides a very convenient way to directly use TTL digital interface to complete high-performance digital to analog conversion below 300 MHz in order to avoid using complex and high-energy ECL circuit. It can be widely used in communication system signal source, digital signal synthesis and intelligent instrument. Its main features are:

(1) Conversion rate 300 ms / S;

(2) Vertical resolution 14 b;

(3) Working voltage 3 V;

(4) Spurious free dynamic range SFDR is 73 DBC (fout = 50.2 MHz, fdata = 150 MHz);

(5) Enter the setup time of 2.0 ns;

(6) Output setup time 11.0 ns;

1. Working principle of ad9755

Ad9755 is mainly composed of two groups of 14 bit data input interfaces, 2-1 multiplexer, DAC latch, reference voltage, PMOS current source array, segmented switcher, PLL circuit and DAC unit. Its internal structure is shown in Figure 1. The 48 pin LQFP package is adopted. In the figure, there are two 14 bit compatible TTL level data input ports. The maximum input frequency of each port is 150 MHz. After the two data streams are latched on the chip, they are synthesized into one 300 MHz parallel data stream through the 2-1 multiplexer, and then latched by the DAC latch and transmitted to the segment switching unit for processing.

Ad9755 has built-in reference voltage source, which saves the trouble of external reference voltage device for conventional high-precision DA conversion chip. The PMOS current source array in Figure 1 is specially designed to ensure the full range output current ioutfs. The size of ioutfs is determined by the internal reference control amplifier and the external resistance RSET. The chip adopts a segmented structure, that is, the data bits are divided into the highest 5 bits, the middle 4 bits and the lowest 5 bits. Different digital to analog conversion methods are adopted for the data of each segment to ensure the accuracy of digital to analog conversion. The segmented switching unit performs correlation processing on the received PMOS current source array output current and the 14 bit data locked by the DAC latch, and then transmits it to the DAC unit of the last stage to realize the whole digital to analog conversion process.

Ad9755 has two working modes: using phase-locked loop (PLL) and not using phase-locked loop, depending on whether the pllvdd pin is connected to power or ground. When the duty cycle of the input clock is not 50%, PLL operation mode can be used. The VCO inside the PLL circuit can form a 100 “400 MHz periodic signal. The user determines the frequency division level of the periodic signal by setting div0 and div1 pins (as shown in Table 2) After the PLL detects the phase of the frequency division signal and the external input clock, it completes the clock frequency locking together with the PLL. When the PLL is not used, the div0 and div1 pins determine the four working states as shown in Table 2. In the interlaced and external frequency doubling mode, the external clock should be twice the input data rate; in the single choice of 1 (or 2) port mode (that is, when only one channel of DA conversion is completed), and in interlaced and internal frequency doubling mode, the external clock shall be set to be consistent with the input data rate.

Ad9755 provides a pair of complementary current outputs iouta and ioutb, which are functions of input data and can be expressed as:

As shown in Figure 1, iouta and ioutb can be directly connected to the analog ground by a 50 Ω resistor (preferably a precision resistor with good temperature characteristics). The final differential output voltage value is: (iouta-ioutb) × 50。

2 Application Design

The following is an example of using ad9755 as a digital to analog converter to generate arbitrary waveform. First, the waveform is edited on the PC. the specific methods can be table page input, mathematical expression or drawing graphics through the mouse. The sine wave, general function or pseudo-random noise are selected by the software, and the amplitude, frequency and offset of the signal are set, and then the waveform data is obtained through rapid calculation. After the waveform data is written into two groups of high-capacity SRAM devices (idt71v3558, maximum working frequency 200 MHz) through PCI card, wait for the Da start command of the upper system.

After the Da is started, the ISP chip (isp2128ve, maximum operating frequency 250 MHz) forms a 75 MHz high-speed address to drive the continuous and parallel output of dual SRAM data. The two output data are respectively transmitted to data port 1 and data port 2 of ad9755. Since the system adopts a high-performance 150 MHz constant temperature crystal oscillator, the working mode of ad9755 is simply set to interlace and external frequency doubling without PLL. The application circuit diagram is shown in Figure 2.

It is worth noting that ad9755 has a more flexible clock access mode. It can be differential access, single ended access, or even directly use the sine wave with Vp-p above 1V. Different access methods should use the corresponding filter network. In order to effectively suppress the spurious level and eliminate the phase noise in the output signal, the high-performance device with good turnover speed should be selected for the processing of clock synchronization; To ensure that the edge of the signal is steep and the front and rear jitter is minimized.

Figure 3 shows the working sequence diagram of ad9755. Since the input data port latch and DAC latch occur on the rising edge of CLK, in order to ensure sufficient data establishment time and data correctness, the data change of the two 14 bit data ports is best completed on the falling edge of CLK. The change time of DAC appears in the third clock cycle, and there is a propagation delay of TPD less than 1ns. It is not difficult to see that the working clock of ad9755 is exactly twice the data change rate, and completes the alternating digital to analog conversion of two data channels in turn. SRAM group I stores odd point data of arbitrary waveform, while SRAM group II stores even point data of waveform. Iouta or ioutb reflects DAC in the same order as the original data.

Due to the extremely rich frequency components of arbitrary waveforms, the appearance of common mode noise and high-order harmonics will inevitably reduce the output signal quality. In order to improve the linearity of Da transform, suppress distortion and noise to the greatest extent, and improve the load capacity of signal source, the output method in Fig. 2 is different from the method of directly connecting 50 Ω to analog ground in Fig. 1, that is, a broadband operational amplifier max4100 (bandwidth of 500MHz) is introduced.

Finally, it should be emphasized that high-speed TTL digital circuit and high-speed analog circuit should also overcome the overshoot and oscillation of the signal through impedance matching as required by ECL circuit. The strip line and microstrip line are designed according to the transmission line theory. The impedance value of PCB connection is related to the thickness of copper foil of circuit board, the filling dielectric material between board layers and its height. See reference 2 for the calculation method. Multilayer board is selected, and the basis for determining the number of circuit board layers is: NL = 5log [anfclk]. Where an is the width of the data bus and fclk is the highest operating frequency.

Responsible editor: GT


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