Ads6125 / ads6124 / ads6123 / ads6122 (ads612x) is a 12 bit a / D converter with sampling frequency up to 125msps, a family. It combines high performance and low power consumption in a compact 32qfn package. The use of internal high bandwidth sample and hold and low jitter clock buffers helps to achieve high SNR and high SFDR even at high input frequencies. It has coarse and excellent gain options for improving SFDR performance in the lower full scale analog input range.
The digital data output is either parallel CMOS or ddrlvds (dual data rate). Several features exist to ease data acquisition, such as – output clock position and output buffer drive and LVDS current and internal terminal programmable control. Output interface type, gain and other functions are programmed with 3-wire serial interface. Alternatively, some of these functions are dedicated and marketed to enable the device to be configured in the desired state after power on.
The ads612x includes an internal reference while eliminating traditional reference pins and associated external decoupling. External benchmark mode is also supported. These devices operate in the industrial temperature range (- 40 ℃) ° C to 85 ° C) Specify.
Ø Maximum sampling rate: 125msps
Ø 12 bit resolution, no loss code
Ø 3.5 DB coarse tuning, up to 6dB programmable gain, fine SNR / SFDR tradeoff
Ø Parallel CMOS and dual data rate (DDR) LVDS output options
Ø Support sine, lvcmos, LVPECL, LVDS clock input and clock amplitude down to 400mvpp
Ø Clock duty cycle stabilizer
Ø Internal reference and external reference support
Ø No references required for external decoupling
Ø Programmable output clock position and driving strength to simplify data acquisition
Ø 3.3V analog and 1.8V to 3.3V digital power supplies
Ø 32qfn package (5 mmol) × 5 mm)
Ø Pin compatible 12 bit home (ads612x)
Editor in charge: GT