Nowadays, DDR3 memory technology in computer system has been widely used, and the data transmission rate has been improved again and again, which is now as high as 1866mbps. Under the condition of this high-speed bus, it is a great challenge for the design and implementation to ensure the reliability of data transmission quality and meet the timing requirements of parallel bus.
This paper mainly uses the time domain analysis tool of cadence company to quantitatively analyze the DDR3 design, introduces the main factors affecting the signal integrity, analyzes the timing of DDR3, improves and optimizes the design through the analysis results, improves the signal quality, and greatly improves its reliability and safety.
2 DDR3 introduction
DDR3 memory is similar to DDR2 Memory, including controller and memory. Both adopt source synchronization timing, that is, the strobe signal (clock) is not sent by an independent clock source, but by the driver chip. It has higher data transmission rate than DR2, up to 1866mbps; DDR3 also adopts 8-bit prefetching technology, which significantly improves the storage bandwidth; Its working voltage is 1.5V to ensure lower power consumption at the same frequency.
DDR3 interface is difficult to design and implement. It adopts a unique fly by topology and uses “write level” technology to control the internal offset timing of the controller. Although it plays a role in ensuring the integrity of design, implementation and signal, it is not comprehensive to realize the storage system with high frequency and high bandwidth. Simulation analysis is needed to ensure the integrity of design, implementation and signal quality.
3 Simulation Analysis
The simulation analysis of DDR3 is described in combination with the project: PowerPC 64 bit dual core CPU module is selected, and the module uses mt41j256m16ha-125it of micron company as the memory. Freescale p5020 analyzes the processor. The module is configured with memory bus, with data transmission rate of 1333mt / s and simulation frequency of 666mhz.
3.1 preparation before simulation
Before analysis, it is necessary to communicate with the PCB manufacturer to confirm the laminated structure of its PCB according to the impedance of DDR3. The key to ensure good transmission linearity in high-speed transmission is the continuity of characteristic impedance. It is determined that the impedance of high-speed PCB signal line is controlled within a certain range to make the printed board become a “controllable impedance board”, which is the basis of simulation analysis. The single line impedance of DDR3 bus is 50 Ω and the differential line impedance is 100 Ω.
Set the voltage value of the analysis network terminal; The components analyzed include passive component allocation model; Determine the device class attributes; Ensure the device pin properties (input ＼ output, power supply ＼ ground, etc.)