Authors: Li Beiguo, Yang Shenglong, Li Huijing

introduction

Compared with traditional TTL interface, LVDS (low voltage differential signal) has low voltage swing, high noise tolerance, and only a few milliwatts of power consumption. Its anti-interference performance is superior to other bus interfaces. However, due to its low-voltage differential transmission, the normal communication distance is only about 5m. At the same time, in the face of complex electromagnetic environment, it will lead to signal transmission error and reduce the transmission reliability. This design greatly improves the communication distance of LVDS signal by adding driver and adaptive equalizer to the transmission interface; at the same time, 10b6b coding mode is adopted in the link, which can detect and correct 1 bit data on the basis of maintaining DC balance, so as to reduce the bit error rate of data transmission to a certain extent, and ensure the high-speed and long-distance transmission of LVDS signal in harsh environment Reliability.

Optimization design of hardware circuit

In engineering application, when the general LVDS interface is used for data transmission, the signal has been seriously attenuated and distorted when the transmission distance is 5 m, so it is unable to distinguish the high and low levels, resulting in high bit error rate.

In LVDS link transmission, the causes of bit error and loss can be analyzed from the following aspects:

(1) When the distance is long, the signal attenuation is serious;

(2) The unbalanced DC in the transmission line leads to the error code;

(3) Clock synchronization error, the clock solved by the receiver is inconsistent with the clock embedded in the sender, resulting in data receiving error.

Through the above analysis, the LVDS interface circuit is optimized in hardware design. At the data sending end, sn65lv1023a serializer is used to convert the parallel data output from FPGA into serial output. Then lmh0001sq high-speed driver is added at the sending end to enhance the signal driving ability. At the receiving end, lmh0073sq adaptive equalizer is used to compensate the attenuation of signal in long-distance transmission and recover the distorted signal. Finally, sn65lv1224bdbr is used to de serialize the signal The serial data is converted into parallel data, and the data is sent to the upper computer for analysis and processing through the PCI interface of the ground test bench. The overall design block diagram of the system is shown in Figure 1.

Optimization design of LVDS receiver circuit based on CPLD

1.1 optimization design of transmitter circuit

In the LVDS transmitter, because the output of sn65lv1023a is only about 100mV low-voltage differential signal, it is necessary to add lmh0001sq driver in the differential output to improve the driving ability. The maximum transmission rate of lmh0001sq high-speed driver is 540mb / s, the differential input threshold voltage is 100mV, and the power consumption is only 125MW. The output voltage can be adjusted through the external resistance of ref pin. This design uses 750 Ω external resistance to get about 800 MV differential voltage output. With DC bias voltage, the output voltage is between 1.6 V and 2.4 V, which improves the driving ability of long-distance data transmission. The design of the transmitter driver is shown in Figure 2.

Because the input resistance of lmh0001sq differential line needs to match the impedance of sn65lv1023a, the 100 Ω resistance should be close to the pin in PCB design; at the same time, the smda03lc interface protection chip is added to the output end, which can prevent the irreversible fault of the output end circuit from affecting the subsequent circuit, and ensure the safety and reliability of LVDS interface.

1.2 optimization design of receiver circuit

In the process of high-speed transmission, LVDS signal will produce certain loss due to the skin effect of conductor. The loss degree is proportional to the square root of signal frequency and the product of cable length. In order to ensure the reliability of receiving signal transmission, the compensation signal is needed. Lmh0074sq equalizer is designed for 78mb / S ~ 540mb / s transmission rate, which can adaptively compensate the transmission loss of 400MB den 1694a and type 5 unshielded twisted pair. The equalizer has very low jitter and power consumption is only 208mw.

The receiver equalizer design is shown in Figure 3. When used, a 1 μ f capacitor is bridged between AEC + and AEC – pins of lmh0074 equalizer to control the gain and bandwidth of equalization loop. Because the output terminal has 50 Ω differential output, in order to prevent the signal ringing or reflection, 100 Ω resistance with 1% accuracy can be matched between the differential lines, and the wiring should be close to the deserializer as far as possible. The equalizer restores the attenuation and distortion signal to the greatest extent, improves the transmission quality of the cable, and reduces the phenomenon of bit error and number loss.

210b6b coding logic design

In order to further improve the reliability of LVDS data transmission, based on the coding idea of (7,4) linear block code, a 10b6b coding method is improved and designed on the basis of the traditional 10b8b coding method. In the case of allowing to reduce the effective bandwidth of transmission, a 4bit supervision bit is designed to correct the 4bit information bit, which greatly reduces the bit error rate of LVDS data transmission and improves the performance of DC balance Status.

2.110b6b coding principle

According to the coding principle of linear block codes, (n, K) block codes require 2r-1 ≥ n (r = n-k), in order to construct r supervision relations with R supervision bits to indicate N possible positions of a bit error, and then realize error control. Because LVDS data transmits 10bit data each time, it needs at least 4bit supervision bits. Therefore, the core of this coding method is to construct four supervision relations with 4bit supervision bits to indicate 10 kinds of bit error locations. The four supervision relations generated by the four bit supervision bits can theoretically generate 16 kinds of correction sub code groups, and select the appropriate correction sub code group according to the actual needs to generate a more suitable code type for transmission.

2.210b6b transmitter logic design

The relationship between the corrector set by the improved 10b6b code and the error location is shown in Table 1, where S1, S2, S3 and S4 represent the corrector calculated by the supervision relation equation. It can be seen from table 1 that when the error location is A6, A8, A0, A2, A3, the corrector S1 = 1; otherwise, S1 = 0. Therefore, there are:

When encoding, A9, A8, a7, A6, A5 and A4 are taken as information symbols, and A3, A2, A1 and A0 are taken as supervision symbols. The information symbols are random, and the supervision symbols are uniquely determined by the following supervision equation:

From the above equation, 64 allowable code groups shown in Table 2 can be obtained.

LVDS data transmission alternates between valid data and invalid data. Each byte of valid data needs to be transmitted twice. The first transmission is 4 bits lower, and the second transmission is 4 bits higher. The highest two bits A9 and A8 of LVDS are used as the high and low bit identification. 0000011111 is sent as invalid data when the data line is idle to lock the transmission clock. The specific definition of LVDS data bits is shown in Table 3.

When the line is idle, the invalid data sent is 000001111, and the invalid code redundancy of 1 bit error code should be considered when coding, that is, the invalid redundancy code shown in Table 4 is treated as invalid code when receiving. Since 0100011111 conflicts with the allowable code group in Table 2, 01 is not used in coding.

Decoding design of 2.310b6b receiver

When the receiving end receives the data, it first calculates the corrector according to the corrector equation. According to table 1, it can correspond to the data error position, and encode the position to generate the error correction code, as shown in Table 5. It should be noted that when the data is received as the data in Table 4, all the codes are considered invalid at this time and no correction calculation is performed. After the error correction code is generated, XOR operation is performed with the received original LVDS data to correct one bit error in the process of data transmission.

The system can also count the amount of error data. When the error correction code is 0000000011, it means that there are two or more dislocations, at this time, the byte error statistics increase by 1; when the error correction code is not 0000000000, it means that there is a bit error in the data, at this time, the data bit error statistics increase by 1, which is convenient for data statistics of the amount of error.

3 clock synchronization logic design

Before data transmission, both transmitter and receiver need to lock the clock synchronously. At initialization, the serializer sn65lv1023a and the deserializer sn65lv1224b are all three state outputs. When the chip power supply voltage is stable to 2.45v, the deserializer starts the PLL to track and lock the local clock to complete the synchronization of the data serializer and the data deserializer.

The synchronization mode of this design adopts the combination of random synchronization and fast synchronization. After the device is powered on, the serializer sn65lv1023a locks the transmit clock TCLK, and the FPGA lowers the level of its SYNC1 and SYNC2 pins. At this time, the serializer sends the synchronization code to the receiver. When the deserializer detects the edge conversion of LVDS input, it will try to lock to the embedded clock according to the REFCLK reference clock provided by FPGA Clock information in the data stream. Since the lock of the serializer sync pin and the deserializer is in the open-loop state, the synchronization time cannot be accurately determined. Therefore, after setting the waiting time of 25 μ s, the deserializer and the serializer complete the synchronization. After sending the solved rCLK clock to the FPGA, the lock pin will automatically pull down to start the data transmission.

During data transmission, when a byte data is repeatedly transmitted, the deserializer may enter into a false locking state and mistakenly identify the rising edge of the data as the start / stop bit. This phenomenon is called repeated multiple transform (RMT) [9]. When the circuit in the deserializer detects the false lock state, the circuit will prevent the lock pin output from being valid until the false lock state changes. When the deserializer detects that the rising edge (stop / start bit) of four consecutive cycles are in the same position, the deserializer will re lock the clock, otherwise it will still be in the out of lock state.

In this design, the data transmission adopts the mode of effective number and invalid number mixed transmission, which can not only ensure the continuous data transmission of LVDS line at all times, but also reduce the number loss caused by the embedded clock bit locking error. At the same time, set the highest two bits as the identification bit. When the highest bit is “10” and “11”, it is the lower 4 bits and the higher 4 bits of the valid data. Otherwise, it is invalid. This kind of high bit fixed value transmission mode greatly reduces the possibility of bit error locking of embedded clock due to the fixed cycle jump after 12bit each time.

4 data reliability verification

The hardware optimization effect is tested. When the length of the twisted pair is 3.5m without adding the driver and equalizer, the data reception is normal; when the length of the cable increases, the bit error rate also increases; when the length of the test transmission cable network increases to 48m, the bit error rate has reached 64.830245%, which can not guarantee the reliable transmission of data.

After the hardware optimization of driver and equalizer is added, the 48m cable network is composed of 6 8m shielded twisted pairs for testing. The LVDS data transmission clock in the acquisition and coding program is modified to make the actual transmission rate of 100MB / s, 200MB / s, 300MB / s and 400MB / s. The error code test is carried out before and after using 10b6b coding mode, and the results are shown in Table 6.

The test results show that when the transmission rate is lower than 100MB / s, the hardware circuit can ensure the reliability of transmission; when the transmission rate is higher than 100MB / s, the bit error rate increases with the increase of the transmission rate. After 10b6b coding is added to the logic design, the reliability of remote LVDS data transmission can be guaranteed when the transmission rate is 400MB / s while the effective bandwidth is allowed to be reduced.

5 Conclusion

Aiming at the reliability problem in LVDS transmission process, the hardware and logic coding methods are optimized. The 10b6b code can detect and correct the 1 bit error data in the data, which ensures the reliability of the data. When testing the data of four code types of “incremental number”, “incremental number”, “all zero number” and “all one number”, it can realize 48m long-distance reliable transmission with zero error code at 400MB / s rate. This design system has been successfully applied in spacecraft.

Editor in charge: GT

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