1、 Introduction

With the increasing complexity of PCB design, in addition to reflection, crosstalk and EMI, stable and reliable power supply has become one of the key research directions of designers. Especially when the number of switching devices is increasing and the core voltage is decreasing, the fluctuation of power supply often has a fatal impact on the system, so people put forward a new term: power integrity, abbreviated as pi (power integrity). In today’s international market, IC design is relatively developed, but power integrity design is still a weak link. Therefore, this paper puts forward the generation of power integrity problem in PCB, analyzes the factors affecting power integrity, and puts forward the optimization method and empirical design to solve the power integrity problem in PCB, which has strong theoretical analysis and practical engineering application value.

2、 Cause and analysis of power supply noise

For the cause of power supply noise, we analyze it through a NAND gate circuit diagram. The circuit diagram in Figure 1 is the structure diagram of a three input NAND gate. Because the NAND gate belongs to a digital device, it works through the switching of “1” and “0” levels. With the continuous improvement of IC technology, the switching speed of digital devices is faster and faster, which introduces more high-frequency components. At the same time, the inductance in the loop is easy to cause power fluctuation at high frequency. As shown in Figure 1, when the NAND gate input is all at high level, the triode in the circuit is turned on, the circuit is short circuited instantly, and the power supply charges the capacitor and flows into the ground wire at the same time. At this time, due to the parasitic inductance on the power line and ground wire, we can know from the formula v = LDI / dt that this will produce voltage fluctuations on the power line and ground wire, as introduced by the rising edge of the level shown in Figure 2 Δ I noise. When the NAND gate input is at a low level, the capacitor will discharge and a large voltage will be generated on the ground wire Δ I noise; At this time, the power supply only has the current mutation caused by the instantaneous short circuit of the circuit. Because there is no charging to the capacitor, the current mutation is smaller than the rising edge. From the analysis of NAND gate circuit, we know that the source of power supply instability mainly lies in two aspects: first, the transient alternating current is too large under the high-speed switching state of the device;

Optimal design of power integrity in PCB

The second is the inductance in the current circuit. The so-called power integrity problem means that in high-speed PCB, when a large number of chips are turned on or off at the same time, a large transient current will be generated in the circuit. At the same time, due to the existence of inductance and resistance on the power line and ground line, voltage fluctuation will be generated on them. Understand the essence of the power integrity problem. We know that to solve the power integrity problem, first of all, for high-speed devices, we add decoupling capacitors to remove its high-frequency noise component, so as to reduce the transient time of the signal; For the inductance in the loop, we should consider the hierarchical design of the power supply.

3、 Application of decoupling capacitor

Decoupling capacitor plays an important role in high-speed PCB design, and its placement position is also very important. This is because when the power supply supplies power to the load for a short time, the stored charge in the capacitor can prevent the voltage from falling. If the capacitor is placed improperly, the line impedance will be too large and the power supply will be affected. At the same time, the capacitor can filter out the high-frequency noise during the high-speed switching of the device. In the high-speed PCB design, we usually add a decoupling capacitor at the output of the power supply and the power input of the chip, in which the capacitance near the power supply is generally large (e.g. 10) μ F) , this is because we generally use DC power supply in PCB. In order to filter the power supply noise, the resonant frequency of capacitor can be relatively low; At the same time, large capacitance can ensure the stability of power output. For the decoupling capacitance added at the pin of the chip connected to the power supply, the capacitance value is generally small (such as 0.1 μ F) , this is because in high-speed chips, the noise frequency is generally high, which requires that the resonant frequency of the decoupling capacitor should be high, that is, the capacitance of the decoupling capacitor should be small.

For the placement of decoupling capacitor, we know that if the position is improper, it will increase the line impedance, reduce its resonant frequency and affect the power supply. For the decoupling capacitor and the inductance in the chip or power supply, we can find the following formula:, in the formula, l: the line length between the capacitor and the chip; r: Line radius; d: Distance between power line and ground;

Therefore, we know that to reduce the inductance L, we must reduce L and D, that is, reduce the loop area formed by the decoupling capacitor and the chip, that is, the capacitor and the chip are required to be as close to the chip device as possible.

4、 Design of power circuit

To ensure the integrity of power supply, we know that a good power distribution network is essential. Firstly, for the design of power line and ground wire, we should ensure that the linewidth is thickened (for example, the width is 40mil, while the common signal line is 10mil), so as to reduce its impedance value as much as possible. With the increasing speed of the chip, according to the 5 / 5 rule, we use more and more multilayer boards to supply power through the special power layer and form a loop through the special layer, which reduces the inductance of the line.

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