In the world of ASIC, the common standard to measure device capacity is equivalent gate. This is because different manufacturers provide different functional modules in the cell library, and the implementation of each functional module requires a different number of transistors. In this way, it is difficult to compare the capacity and complexity between the two devices.

The solution is to give each function an equivalent gate value, such as “function module a is equivalent to 5 equivalent gates, and function module B is equivalent to 3 equivalent gates”. The next step is to count each functional module, convert them into corresponding equivalent gate values, add these values, and then proudly announce: “my ASIC includes 10 million equivalent gates, which is much more than your ASIC!”

However, things are not so simple. Different manufacturers have different definitions of the actual structure of peer-to-peer gates. Typically, a 2-input NAND function represents an equivalent gate. Some manufacturers also define an equivalent gate equivalent to a specific number of transistors. Other manufacturers define an ECL equivalent gate as “1 / 11 of the minimum logic required to realize a single bit full adder” (who came up with this?). Usually, the best way is to make sure everyone is talking about the same thing before investing.

Back to FPGA, FPGA manufacturers encountered a problem. They tried to establish a foundation for comparing their devices with ASICs. For example, if someone has a ready-made ASIC design containing 500000 equivalent gates and wants to implement the design with FPGA, how should he describe the FPGA required for the design? In fact, each 4-input LUT can represent any function that can be represented by more than 1 to 20 2-input basic logic gates, so this comparison is quite microseconds.

On logic gate and system gate in FPGA

In order to solve this problem, FPGA manufacturers began to discuss system gates in the early 1990s. Some people say that this is a costly idea, and this special term will be involved in ASIC design. Others say that this is purely a market strategy and does no good to anyone.

Unfortunately, there seems to be no clear definition to explain what a system gate is. This is embarrassing when FPGA essentially contains only general programmable logic resources in the form of LUT or register. At that time, it was even difficult to define whether a special ASIC design containing x equivalent Gates could be replaced by an FPGA containing y system gates. This is because some ASIC designers may have advantages in combinatorial logic, while others may prefer to use registers. The results obtained in these two cases may not be an optimal mapping on FPGA.

When FPGA begins to include embedded RAM blocks, the problem becomes particularly serious, because some functions are implemented using ram more efficiently than general logic. Moreover, in fact, LUT can be used as distributed ram. For example, the calculated value of some manufacturers’ system gates now includes an attribute, “it is assumed that 20% ~ 30% of LUT is used as RAM”. Of course, this problem becomes more serious when we begin to think that FPGA includes embedded processor core and similar functions. Therefore, some manufacturers now say that “the system gate value is not included in these components”.

Is there a simple rule to convert a system gate into an equivalent gate? In fact, there are many. Some people think that if you feel optimistic, you should divide the system gate value by 3 (for example, 3 million FPGA system gates should be equal to 1 million ASIC equivalent gates). Or if you feel more pessimistic, you can divide the system gate by 5 (so that 3 million system gates will be equal to 600000 equivalent gates).

However, some people believe that the above rule is correct only when you assume that the system gate value includes all functions that can be implemented using general programmable logic and block ram. These people will continue to say that if you remove ram from the equation, you must divide the system gate value by 10 (at this time, 3 million system gates can only be equal to 300000 equivalent gates), but you can still use block ram.

Finally, this problem falls into such a quagmire that even FPGA manufacturers are reluctant to talk about system gates. For the new FPGA in people’s vision, people are comfortable imagining the equivalent gate, and it is convenient to consider the design with LUT, slice, etc. However, a large number of FPGA designers are more accustomed to using the term FPGA. For this reason, some people still retain the traditional habit. What I prefer to see is that I prefer to use the following simple numbers to specify and compare FPGAs:

Logical unit, logical element or other; Number of embedded block ram; Number of embedded multipliers; Number of embedded adders; Number of embedded Macs; other.

Why is it so difficult? It is very useful to comprehensively describe an ASIC design example in the real world and give their equivalent gates, including their registers / latches, primitive gates and other more complex functions. These design examples are related to the number of LUTS and registers / latches required to implement in FPGA, as well as the number of embedded RAM and other embedded functions. Although it is not ideal now, because people’s design is different in FPGA and ASIC, there will always be a beginning.


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