Image sensor is developing towards SOS (system on sensor). The leading comprehensive advantage is no longer expressed. With the comprehensive improvement of image resolution, the traditional DSP has been unable to meet the requirements of high performance, low power consumption, small area and low cost. Therefore, choosing RDSP (reconfigurable digital signal processing) is a better answer, which can solve the above comprehensive problems. RDSP system has the advantages of intelligent dynamic adjustment of the number of cores, dynamic adjustment of working frequency, configuration algorithm accelerator, game router, dynamic memory management and other technologies.
RDSP (reconfigurable digital signal processing) is based on massively parallel processing technology. Its instruction set architecture is designed for computing intensive image / video processors. Each RDSP unit core contains a 24 bit multiplier, 16 bit logic unit, 40 bit accumulator and 40 bit shifter, supporting floating-point, reciprocal and square root acceleration. Based on 8-bit SIMD (single instruction multiple data) structure, 16 bit fixed-point and 32-bit floating-point operations can be realized.
The assembly language of RDSP uses easy-to-use and reliable algebraic syntax coding. The optimized architecture can be combined with C compiler to achieve fast and efficient software compilation. Each unit is based on a Harvard architecture model with separate instruction and data memory. The operands that perform the operation come from memory, instruction constant fields, and internal registers. The internal registers include 16 independent 16 bit GPRS (general purpose registers), the pointer supports four independent 16 bit registers, 1K bytes shared storage layer, 2K bytes CDR (competitive data routing) direct addressing, and supports mark index offset, base addressing and general functions.
CDR provides data storage, control logic, registers and fast routing services, and related data is processed by resource router. This architecture meets the requirements of intelligent analysis and management, multi topology network on chip, independent and transparent processing of data resources, real-time programmable and adaptable communication structure, and supports any network routing function or intelligent topology link.
The new generation of SOS thermal imaging sensor of Xinfu company will adopt this original architecture. The ASIC circuit meets the requirements of 28nm ~ 90nm process, and the chip area is very small. Under the calculation condition of 3000ips, the power consumption is 90mw ~ 150MW, which can meet dozens of real-time image processing algorithms of thermal imaging sensor. It is especially suitable for running the standard algorithm based on “artificial intelligence” theoretical model.
Editor in charge: PJ