Today’s signal processing systems generally require the use of mixed-signal devices such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and fast signal processors (DSPs). In order to handle analog signals with a wide dynamic range, high-speed and high-performance ADC and DAC signals are more important. To maintain the wide dynamic range and low noise of analog signals in harsh digital environments, good high-speed circuit design techniques are used, including proper signal routing, decoupling, and grounding.

In the past, “high-precision, low-speed” circuits were generally viewed as distinct from so-called “high-speed” circuits. For ADCs and DACs, the sampling rate (for ADCs) and the update rate (for DACs) serve as criteria for dividing what is called “high speed” and “low speed”. However, the following two examples show that most signal processing chips today are truly “high-speed” chips and must be treated as high-speed devices in order to maintain their high performance. Such as DSP and AD/DA chips.

Sampling ADCs (ADCs with internal sample-and-hold circuits) for all signal processing applications operate with relatively high-speed clocks. This clock has fast rise and fall times (typically a few nanoseconds), so it must be considered a high-speed device, even though the slew rate may be low. For example, a mid-speed 12-bit successive approximation (SAR) ADC operates on an internal clock of 10MHz, while sampling at only 500 KSPS. Sigma-delta ADCs also require high-speed clocks because of their high oversampling rates. Even high-resolution, so-called “low frequency” industrial measurement sigma-delta ADCs (with a throughput of 10 Hz to 7.5 kHz) operate at clock frequencies of 5MHz or higher to provide 24-bit resolution (for example, ADI company’s AD77xx-series). To complicate matters, mixed-signal ICs have both analog and digital ports, so it’s even more confusing how to use proper grounding techniques. In addition, some mixed-signal ICs have relatively low digital currents, while others have high digital currents. In many cases, the two types must be treated separately for optimal grounding.

Digital and analog design engineers tend to approach mixed-signal devices from different perspectives, and the purpose of this tutorial is to summarize a general grounding principle that can be used for most mixed-signal devices without knowing the specifics of their internal circuitry.

ground and power planes

A low-impedance, large-area ground plane is critical for both analog and digital circuits. The ground plane is designed not only to give high frequency currents (generated by high speed digital logic) a low impedance return path, but also to minimize EMI/RFI emissions. The circuit is also less susceptible to external EMI/RFI due to the shielding effect of the ground plane.

The ground plane also allows high-speed digital or analog signals to be transmitted using transmission line technologies (microstrip or stripline) that require controlled impedance.

Since the “buss wire” has impedance at the equivalent frequency of most logic transitions, its use as “ground” is totally unacceptable. For example, #22 standard wire has an inductance of about 20 nH/inch. A transient current with a slew rate of 10mA/ns produced by the logic signal, flowing 1 inch through this wire at this frequency will create an unwanted voltage drop of 200 mV:

For a signal with a 2 V peak-to-peak range, this voltage drop translates to an error of about 10% (about 3.5 bits of accuracy). Even in an all-digital circuit, this error can cause a significant drop in the noise margin of the logic circuit.

Figure 1: Digital current flowing into the analog return path creates an error voltage

Figure 1 shows a typical example of digital return current interfering with analog return current (top graph). The wire inductance and resistance of the ground path is shared by the analog and digital circuits, which can interact with each other and ultimately create errors. A possible solution is to have the digital circuit current return path flow directly to the GND REF, as shown in the bottom image. This is the basic principle of “star grounding” or single-point grounding. Achieving true single-point grounding in systems containing multiple high-frequency return paths is difficult because the physical length of the individual current-return-path wires introduces parasitic resistance and inductance that do not comply with the low-impedance grounding principle for high-frequency currents . In practice, the current loop must consist of a large-area ground plane in order to achieve a low-impedance ground at high-frequency currents. Without a low-impedance ground plane, it is nearly impossible to avoid the shared impedance described above, especially at high frequencies.

All IC ground pins should be connected directly to a low impedance ground plane to minimize series inductance and resistance (meaning no IC sockets or anything like that). For high-speed devices, traditional IC sockets are not recommended. Even for “small form factor” sockets, additional inductance and capacitance can introduce useless shared paths that can disrupt device performance. Individual “pin sockets” or “cage sockets” are acceptable if sockets must be used with DIP packages, such as when prototyping. The above pin sockets are available in capped and uncapped versions (AMP part numbers 5-330808-3 and 5-330808-6). Thanks to the use of spring metal contacts, a good electrical and mechanical connection to the IC pins is ensured. However, repeated insertion and removal may degrade its performance.

Decoupling of low and high frequencies

Each power supply should be decoupled to a low impedance ground plane through a bulk electrolytic capacitor as it enters the PC board, with the electrolytic capacitor close to the power supply terminals. This minimizes low frequency noise on the power line. In each independent analog stage, the power pins of each IC package need local filtering only for high frequencies (meaning the 104 capacitor bypass chip we commonly use, note that 100nF is not used in all cases. 100nF is used below 20MHz, the higher the frequency The higher the capacitance, the smaller).

Figure 2: Local high-frequency power filters provide optimal filtering and decoupling with short, low-inductance paths (ground planes)

Figure 2 shows this method with the correct implementation on the left and the wrong implementation on the right. In the example on the left, a typical 0.1 μF ceramic chip capacitor is connected directly to the ground plane on the backside of the PCB via a via, and to the GND pin of the IC via a second via. In contrast, the setup on the right is less than ideal, adding additional PCB trace inductance to the ground path of the decoupling capacitor, making it less effective. (It is better if the chip capacitors are placed directly under the back of the chip.)

All high-speed chips (frequency greater than 10MHz) require bypass capacitors similar to those connected in Figure 2 to achieve good performance. Magnetic beads are not 100% necessary here, but they will enhance the isolation and decoupling of high frequency noise and are usually beneficial. It may be necessary to verify that the beads will not saturate when the IC handles high currents.

Note that with some beads some may be nonlinear even before saturation occurs, so this should also be checked to verify if the power stage is required to operate with low distortion output.

Double and Multilayer PCBs

Each PCB should have at least one complete layer dedicated to grounding. Ideally, one side of a double-sided board should be used entirely for the ground plane and the other side for interconnects. In practice, however, this is not possible because parts of the ground plane must be removed for signal and power crossovers, vias, and vias. Nevertheless, the area should be saved as much as possible, at least 75%. After the initial layout is complete, double-check the ground plane to make sure there are no isolated ground “islands” (like dead copper), as the IC ground pins located within the ground “islands” have no current return path to the ground plane. Also check for weak connections between adjacent large areas of the ground plane, which may greatly reduce the effectiveness of the ground plane. Undoubtedly, automatic routing techniques are generally not suitable for mixed-signal board designs, so manual routing is highly recommended

In systems that are densely integrated from surface mount ICs, there are a large number of interconnects that necessitate the use of multi-layer circuit boards. In this way, at least an entire layer can be dedicated to grounding. A simple 4-layer board has internal ground and power planes, and two outer layers for interconnection of surface mount components. Having the power and ground planes next to each other provides additional interlayer capacitance (no discrete components currently have the effect of interlayer capacitance), which aids high frequency decoupling of the power supply. In most systems, 4 layers are not enough, and additional layers are needed for signal and power routing.

Multi-card mixed-signal system

In a multi-card system, the best way to reduce ground impedance is to use a “motherboard” PCB as the backplane for inter-card interconnections, thus providing a continuous ground plane for the backplane. At least 30 to 40% of the pins of the PCB connector should be dedicated to ground, and these pins should be connected to the ground plane on the backplane motherboard.

Figure 3: Multipoint Grounding Concept

Finally, there are two possible ways to implement an overall system grounding scheme:

1. The backplane ground layer can be connected to the chassis ground through multiple points, thereby spreading various ground current return paths. This method is often referred to as a “multi-point” grounding system, as shown in Figure 3.

2. The ground plane can be connected to a single system “star ground” point (usually at the power supply).

The first method is most commonly used in all-digital systems, but can be used in mixed-signal systems, provided the ground currents generated by the digital circuits are low enough and spread over a large area. The PC board, backplane, and chassis all maintain low-resistance paths. However, good electrical contact is critical where the ground connects to the sheet metal chassis. This requires self-tapping screws (that is, the usual point-head screws that get tighter every month) and snap washers. Special care must be taken when using anodized aluminum as the case material (that is, the case surface is coated with a layer of aluminum oxide, which is non-conductive). At this time, the case surface is an insulator (meaning this method is not feasible).

The second method (“star ground”) is commonly used in high-speed mixed-signal systems with separate analog and digital ground systems, and requires further discussion.

Separate analog and digital ground planes

In mixed-signal systems that use a large number of digital circuits, it is best to physically separate sensitive analog components from noisy digital components. It is also beneficial to use separate ground planes for analog and digital circuits. Avoiding overlap minimizes capacitive coupling between the two. The separate analog and digital ground planes continue on the backplane through a motherboard ground plane or “ground mesh” (composed of a series of wired interconnects between the connector ground pins). As shown in Figure 4, the two layers remain separated until they return to a common system “star” ground, typically at the power port. The connections between the ground plane, power, and “star” ground should consist of multiple bus bars or wide copper ribbons for minimal resistance and inductance. Back-to-back Schottky diodes are inserted on each PCB to prevent accidental DC voltages between the two ground systems when cards are inserted or removed. This voltage should be less than 300 mV to avoid damage to ICs connected to both the analog and digital ground planes. Schottky diodes are recommended for their low capacitance and low forward voltage drop. Low capacitance prevents AC coupling between analog and digital ground planes. Schottky diodes start to conduct at about 300 mV, and several diodes in parallel may be required if high currents are expected. Ferrite beads can replace Schottky diodes in some cases, but introduce DC ground loops that can be troublesome in high-precision systems.

Figure 4: Separate analog and digital ground planes

The impedance of the ground plane must be as low as possible until it returns to the system star ground. DC or AC voltages above 300 mV between the two ground planes can not only damage the IC, but also cause false triggering and possible latch-up of logic gates.

Grounding and Decoupling for Mixed-Signal ICs with Low Digital Currents

Sensitive analog components such as amplifiers and voltage references are always referenced and decoupled to the analog ground plane. ADCs and DACs (and other mixed-signal ICs) with low digital currents should generally be considered analog devices and can also be grounded and decoupled to the analog ground plane. At first glance, this requirement may seem contradictory, since converters have analog and digital interfaces, and often have pins designated as analog ground (AGND) and digital ground (DGND). The diagram in Figure 5 helps explain this apparent dilemma.

Figure 5: Proper Grounding for Mixed-Signal ICs with Low Internal Digital Currents

Inside ICs that have both analog and digital circuits, such as ADCs or DACs, the ground ports are usually kept separate to avoid coupling digital signals into the analog circuits. Figure 5 shows a simple converter model. Connecting the die pads to the package pins will inevitably result in wire bonding inductance and resistance, which IC designers can do nothing about, just be aware of it. The rapidly changing digital current produces a voltage at point B and is bound to couple to point A of the analog circuit through the stray capacitance CSTRAY. In addition, there is about 0.2pF of stray capacitance between each pin of the IC package, which is also unavoidable! The task of the IC designer is to rule out this effect and make the chip work properly. However, to prevent further coupling, AGND and DGND should be connected together externally with the shortest possible trace to the analog ground plane. Any additional impedance within the DGND connection will generate more digital noise at point B, which in turn will couple more digital noise to the analog circuitry through stray capacitance. Note that connecting DGND to the digital ground plane imposes VNOISE across the AGND and DGND pins, causing serious problems!

The “DGND” designation on the IC means that this pin is connected to the IC’s digital ground, but it doesn’t mean that this pin must be connected to the system’s digital ground.

This arrangement does potentially inject a small amount of digital noise into the analog ground plane. But these currents are very small and can be minimized by making sure that the converter output does not drive a large fanout (which is usually not the case). Minimizing fanout on the converter’s digital ports also makes converter logic transitions less susceptible to ringing and minimizes digital switch currents, thereby reducing the potential for coupling into the converter’s analog ports. The logic supply pin (VD) can be further isolated from the analog supply by inserting a small lossy ferrite bead, as shown in Figure 5. The internal transient digital current of the converter will flow in a small loop from VD through the decoupling capacitor to DGND (this path is represented by the thick solid line in the diagram). Therefore, transient digital currents do not appear on the external analog ground plane, but are confined within the loop. The VD pin decoupling capacitor should be installed as close as possible to the converter to minimize parasitic inductance. These decoupling capacitors should be low inductance ceramic types, typically between 0.01 μF and 0.1 μF.

Handle ADC digital outputs with care

Placing buffer registers next to the converter, as shown in Figure 5, is a good way to isolate the converter digital lines from noise on the data bus. The buffer registers also help minimize loading on the converter’s digital outputs, while providing Faraday shielding between the digital outputs and the data bus. Although many converters have 3-state outputs/inputs, this isolation register represents a good design practice. In some cases, it may be necessary to add additional buffer registers on the analog ground plane next to the converter output to provide better isolation.

A series resistance (labeled “R” in Figure 5) between the ADC output and the buffer register input helps minimize digital transient currents that can affect converter performance. The resistor isolates the digital output driver from the capacitance at the buffer register input. Additionally, an RC network consisting of a series resistor and buffer register input capacitor acts as a low-pass filter to slow down fast edges.

A typical CMOS gate combined with PCB traces and vias will generate a load of about 10 pF. Without the isolation resistor, a logic output slew rate of 1 V/ns would result in a dynamic current of 10 mA:

When driving a 10 pF register input capacitance, a 500 Ω series resistor minimizes this output current and yields rise and fall times of about 11 ns:

TTL-type buffer registers have high input capacitance, which can significantly increase the dynamic switching current and should be avoided.

Buffer registers and other digital circuits should be grounded and decoupled to the digital ground plane of the PC board. Note that any noise between the analog and digital ground planes reduces the noise margin on the converter’s digital interface. Since digital noise immunity is in the hundreds or thousands of millivolts, it is generally unlikely to be a problem. The analog ground plane noise is usually not high, but if the noise on the digital ground plane (relative to the analog ground plane) exceeds hundreds of millivolts, steps should be taken to reduce the digital ground plane impedance to keep the digital noise margin within acceptable limits. s level. Under no circumstances should the voltage between the two ground planes exceed 300 mV, otherwise the IC may be damaged.

It is also best to separate the power supplies for the analog and digital circuits, even if they are the same voltage. The analog power supply should be used to power the converter. If the converter has a designated digital supply pin (VD), it should be powered from a separate analog supply, or filtered as shown. All converter power pins should be decoupled to the analog ground plane, and all logic circuit power pins should be decoupled to the digital ground plane, as shown in Figure 6.

Figure 6: Ground and Decoupling Points

In some cases it is not possible to connect VD to an analog supply. Some newer high-speed ICs may use a +5 V supply to power the analog circuits and a +3 V supply to power the digital interface to interface with 3 V logic. In this case, the +3 V pin of the IC should be decoupled directly to the analog ground plane. It is also recommended to place a ferrite bead in series with the power traces to connect the pins to the +3 V digital logic supply.

The sample clock generation circuit should be treated the same as the analog circuit, also grounded and deeply decoupled to the analog ground plane. Phase noise on the sampling clock can degrade system SNR and is discussed below.

Sample Clock Considerations

In high-performance sampled data systems, where a low phase noise oscillator should be used to generate the ADC (or DAC) sampling clock, sampling clock jitter interferes with analog input/output signals and increases the severity of noise and distortion. The sampling clock generator should be isolated from noisy digital circuits, grounded and decoupled to the analog ground plane, as with op amps and ADCs. The effect of sampling clock jitter on the ADC signal-to-noise ratio (SNR) can be approximated by the following equation:

The only source of noise comes from the rms sampling clock jitter tj. Note that f in the above formula is the analog input frequency. As a simple example, if tj = 50 ps rms, f = 100 kHz, then SNR = 90 dB, which equates to about 15 bits of dynamic range. This effect of clock jitter on SNR is discussed in detail in tutorial MT-007. However, in most high-performance ADCs, the internal aperture jitter is negligible compared to the jitter on the sampling clock.

Ideally, the sample clock oscillator should be referenced to an analog ground plane in a split ground system. However, due to system limitations, this method may not be feasible. In many cases, the sampling clock must be derived from a higher frequency, multipurpose system clock generated on the digital ground plane, which must then be passed from the origin on the digital ground plane to the ADC on the analog ground plane. Ground noise between the two layers adds directly to the clock signal and creates excessive jitter. Jitter can cause a reduction in the signal-to-noise ratio and can also produce interfering harmonics.

Figure 7: Sampling Clock Distribution from Digital-to-Analog Ground Plane

This problem can be solved to some extent by transmitting the sampling clock signal as a differential signal using a small RF transformer or a high-speed differential driver and receiver IC as shown in Figure 7. Many high-speed ADCs have differential sampling clock inputs to facilitate this approach. If using active differential drivers and receivers, choose ECL, low-level ECL, or LVDS to minimize phase jitter. In a +5 V single-supply system, the ECL logic can be connected between ground and the +5 V (PECL) supply and AC-couple the output to the ADC sampling clock input. In either case, the original main system clock must be generated from a low phase noise oscillator, not the clock output of a DSP, microprocessor or microcontroller.

To facilitate system clock management, Analog Devices offers a range of clock generation and distribution products and a complete set of phase-locked loop (PLL) solutions.

The Origins of Mixed-Signal Grounding Confusion: Applying Single-Card Grounding Concepts to Multi-Card Systems

Most ADC, DAC, and other mixed-signal device data sheets discuss grounding for a single PCB, usually the manufacturer’s own evaluation board. Applying these principles to a multi-card or multi-ADC/DAC system can be confusing. It is generally recommended to divide the PCB ground plane into an analog layer and a digital layer. It is also recommended to connect the AGND and DGND pins of the converter together, and connect the analog and digital ground planes at the same point, as shown in Figure 8. This essentially creates a system “star” ground on mixed-signal devices.

Figure 8: Mixed-Signal IC Grounding: Single PC Board (Typical Evaluation/Test Board)

All noisy digital currents flow through the digital power supply to the digital ground plane and back to the digital power supply; isolated from the sensitive analog parts of the board. System star ground structures occur in mixed-signal devices where the analog and digital ground planes are connected together. This method is generally used for simple systems with a single PCB and a single ADC/DAC, and is generally not suitable for multi-card mixed-signal systems. In systems with several ADCs or DACs on different PCBs (or the same PCB where applicable), the analog and digital ground planes are connected at several points, making it possible to create ground loops, whereas single-point “star” ground systems is not possible. For the above reasons, the single-point ground method is not suitable for multi-card systems and should be used for mixed-signal ICs with low digital currents.

Grounding of mixed-signal devices with low digital current in multi-card systems

Figure 9 summarizes the above grounding method for mixed-signal devices with low digital currents. The analog ground plane is not destroyed due to the small digital transient current flowing into the small loop between the decoupling capacitors VD and DGND (shown as a thick solid line). Mixed-signal devices are suitable for all applications as analog components. Noise VN between ground planes reduces the noise margin on the digital interface, but generally has no adverse effect if kept below 300 mV using low impedance digital ground planes all the way back to the system star ground.

Figure 9: Grounding for Mixed-Signal ICs with Low Internal Digital Currents: Multiple PC Boards

However, mixed-signal devices with on-chip analog functions, such as sigma-delta ADCs, codecs, and DSPs, are increasingly digitally integrated. Coupled with other digital circuits, the digital current and noise are getting bigger and bigger. For example, a sigma-delta ADC or DAC contains complex digital filters that can significantly increase the digital current in the device. The above method relies on decoupling capacitors between VD and DGND to isolate digital transient currents in small loops. Here, if the digital currents are too large and have DC or low frequency components, the decoupling capacitors may be too large to be feasible. Any digital current flowing outside the loop between VD and DGND must flow through the analog ground plane. This can reduce performance, especially on high-resolution systems.

It is difficult to predict how much digital current flowing through the analog ground becomes unacceptable. At the moment we can only recommend alternatives that may work better.

Grounding of mixed-signal devices with high digital currents in multi-card systems

An alternative grounding method for high digital current mixed-signal devices is shown in Figure 10. AGND of mixed-signal devices is connected to the analog ground plane, while DGND is connected to the digital ground plane. The digital currents are isolated from the analog ground plane, but the noise between the two ground planes is applied directly between the AGND and DGND pins of the device. In order to successfully implement this method, the analog and digital circuits within the mixed-signal device must be sufficiently isolated. The noise between the AGND and DGND pins should not be too large to reduce the internal noise margin or damage the internal analog circuits.

Figure 10: Alternative Grounding Method for Mixed-Signal ICs with High Digital Currents: Multiple PC Boards

Figure 10 shows an optional Schottky diode (back-to-back) or ferrite bead connecting the analog and digital ground planes to connect the analog and digital grounds. Schottky diodes prevent large DC voltage or low frequency voltage spikes across the two layers. If these voltages exceed 300 mV, they can damage mixed-signal ICs because they appear directly between the AGND and DGND pins. As an alternative to back-to-back Schottky diodes, ferrite beads provide a DC connection between the two layers, but at frequencies above a few MHz, the ferrite beads become resistive, causing isolation. This protects the IC from the DC voltage between AGND and DGND, but the DC connection provided by the ferrite bead may introduce an unwanted DC ground loop and may not be suitable for high-resolution systems.

When the AGND and DGND pins are separated in special ICs with high digital currents, try to connect them together if necessary. With patch cords or strips, you can try both approaches and see which provides the best overall system performance.

Grounding Summary

There is no single method of grounding that will always guarantee 100% optimal performance! This section presents several possible options based on the characteristics of the particular mixed-signal device under consideration. But when implementing the initial PC board layout, it can be helpful to provide as many options as possible. (For example, setting some connection points, testing the impact of connection and disconnection on the system during the experiment)

The PC board must have at least one layer dedicated to the ground plane! Initially draw the board layout to ensure non-overlapping analog and digital ground planes, and if needed, provide pads and vias in multiple locations for mounting back-to-back Schottky diodes or ferrite beads. It is also extremely important to provide pads and vias, and jumpers can be used to connect the analog and digital ground planes together if needed. Currently, predicting whether a “multipoint” (single ground plane) or “star” grounding (separate analog and digital ground plane) approach will provide the best overall system performance is difficult; some experiments.

If you don’t feel confident, it’s better to separate the analog and digital ground planes and jumper them later, rather than start with a single ground plane and try to separate later!

Some general PC board layout guidelines for mixed-signal systems

Obviously, careful consideration of the system layout and preventing different signals from interfering with each other can minimize noise. High-level analog signals should be isolated from low-level analog signals, and both should be kept away from digital signals. We have found in waveform sampling and reconstruction systems that the sampling clock (digital signal) is just as susceptible to noise as analog signals, and just as prone to noise as digital signals, and must therefore be isolated from both analog and digital systems. If clock driver packages are used in clock distribution, only one frequency clock should pass through a single package. Sharing drivers between clocks of different frequencies within the same package will create excessive jitter and crosstalk, and degrade performance.

Where sensitive signals pass through, the ground plane acts as a shield. Figure 11 shows a good layout for a data acquisition board, where all sensitive areas are isolated from each other and signal paths are kept as short as possible. While the actual layout is unlikely to be this neat, the basic principles still apply.

Figure 11: Separate analog and digital circuits in PCB layout

There are many points to consider when making signal and power connections. First, the connector is one of several places in the system where all signal transmission lines must be paralleled, so they must be separated from the ground pins (forming a Faraday shield) to reduce coupling between them.

There are many points to consider when making signal and power connections. First, the connector is one of several places in the system where all signal transmission lines must be paralleled, so they must be separated by ground pins (forming a Faraday shield) to reduce coupling between them. (Explain this paragraph, the connector refers to the kind of FPC cable, all the signals in these signals are connected in parallel, and a ground wire is defined for every other signal line to isolate the signals well. interference)

There is another reason why multiple ground pins are important: it reduces the ground impedance at the junction between the board and the backplane. For new boards, the single pin contact resistance of the PCB connector is very low (10 mΩ level), and as the board gets older, the contact resistance may increase and the performance of the board will be affected. It is therefore necessary to increase the ground connection by assigning additional PCB connector pins (about 30 to 40% of all pins on the PCB connector should be ground pins). For the same reason, each power connection should have several pins, although it doesn’t have to be as many as the ground pins.

Analog Devices and other high-performance mixed-signal IC manufacturers offer evaluation boards to assist customers with initial evaluation and layout. ADC evaluation boards typically contain an on-chip low-jitter sampling clock oscillator, output registers, and appropriate power and signal connectors. There are additional support circuits such as ADC input buffer amplifiers and external reference voltages.

The evaluation board layout has been optimized for grounding, decoupling, and signal paths and can be used as a model for the ADC PC board layout within the system. The actual evaluation board layout is usually provided by the ADC manufacturer as a computer CAD file (Gerber file). In many cases, the device data sheet provides the layout of the layers.

Authors: Walt Kester, James Bryant, Mike Byrne

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