The microcontroller is the heart of the human-machine interface, translating sensor data into commands. The performance improvements brought by process technology and system architecture enable microcontrollers and FPGAs to handle more graphics and audio through hardware engines or software libraries, and provide richer interfaces in industrial environments.

Increased microcontroller integration and cost reductions are driving the technology to further control human-machine interfaces in industrial designs. The ability to integrate an LCD controller and higher performance digital signal processing allows the implementation and display of more complex displays, including 3D graphics, while keeping cost and power consumption as low as possible. Adding additional features, such as touchscreen controllers and communication modules, enables more integration and makes the interface controller a key element in the system.

ARM produces a new generation of processor cores, such as the Cortex-M3 and Cortex-M4, which have significantly higher levels of performance and DSP support, and allow new microcontrollers to handle a wide range of interface functions.

However, there are other ways to approach the challenge. Existing cores can be supplemented with dedicated graphics hardware to take advantage of existing software, while using field programmable gate arrays can provide dedicated hardware or optimized microcontrollers, both combined with the technology that drives the display.

Freescale Semiconductor's KineTIs K40 is a microcontroller designed directly for industrial human machine interfaces. It has a hardware touch-sensitive interface with up to 16 inputs that avoids software polling methods and a flexible low-power LCD controller that supports up to 320 segments (40 x 8 or 44 x 4). The LCD flicker mode enables low average power consumption while maintaining a low power mode, while the segmentation fault detection module prevents false readings and reduces LCD test costs.

The segment LCD controller supports up to 40 fronts and 8 backs, or 44 fronts and 4 backs, all of which can be configured in software to avoid costly display redesigns.

It uses an ARM Cortex-M4 core with DSP instructions, runs at 100 MHz, provides 1.25 Dhrystone MIPS per MHz, and has up to 512 KB of program flash. In addition, 10 low-power modes provide power optimization based on application requirements. There is also a memory protection unit with multi-master protection and a 16-channel DMA controller supporting up to 64 request sources.

An interface needs to collect data from multiple sources. Therefore, two 16-bit SAR ADCs and a Programmable Gain Amplifier (PGA) (up to x64) are integrated into each ADC, along with a 12-bit DAC and three containing a 6-bit DAC and programmable reference input.

To communicate with the rest of the system, the device includes a USB full-speed/low-speed On-the-Go controller via an on-chip transceiver as well as two Controller Area Network (CAN) modules, three SPI modules, two I2C modules, Five UART modules and one I2S module. This means that the device can act as a hub not only for the interface, but also for the rest of the system.

Fujitsu's Graphics Display Controller (GDC) uses an ARM926 core-based SoC architecture. The MB86R01 uses Fujitsu's mature MB86296 3D graphics core and uses Fujitsu's standard 90nm process to provide the best balance of power (low leakage current) and performance.

The MB86R01 graphics SoC uses a layered bus system that isolates high-performance functions such as 3D graphics processing from regular operations such as low-speed I/O. Additionally, ARM processors are designed to run at twice the speed of the graphics core to reduce memory bus contention between these two primary functions.

Figure 1: Fujitsu's MB86R01 graphics SoC.

At the heart of the MB86R01 architecture is a complete 3D geometry processing unit capable of performing all major 3D operations, including transforms, rotations, backface culling, view plane clipping and hidden surface management.

The device has a display controller, supports two capture sources (YUV/ITU656 or RGB), and supports zoom-in and zoom-out of video images. Video can also be mapped to any of the six display layers, and texture-mapped to polygons to create special effects.

The display controller also features dual digital outputs to support multiple display configurations with different resolutions. The content of each panel can be the same or unique. The six display layers of the MB86R01 can be thought of as six separate framebuffers or separate canvases, each of which may contain unique content. These layers can be optimized for size to save memory and improve system throughput and graphics performance. Consider an example of a menu bar. If the actual graphics area is only 60 x 400 pixels, the device allows the layer to be set to match the 60 x 400 display area, and the underlying layer may be full resolution up to 1080 x 768. GDC mixes content in real-time via rendering or block transfer after layers are created,

In addition to multiple layers, Fujitsu GDC offers a variety of alpha blending and transparency options that designers can use to create special effects and improve antialiasing of bitmaps and fonts, making the interface easier to use.

The device also includes a variety of interfaces, from SD card and IDE to USB, SPI, UARTS and Flash/SRAM ports. ADCs and DACs are also included to capture data.

There are other ways to use microcontrollers to build human-machine interfaces. Altera's DK-DSP-3C120NCyclone III development kit allows designers to integrate a 32-bit NIOS processor core with a graphics engine and LCD controller module, both of which can be precisely tuned to the requirements of the application. The low-cost Cyclone III family of FPGAs allows the exact requirements of a design to be implemented in a cost-effective manner.

The NIOS II processor can be configured with additional instructions written specifically to enhance graphics applications by allowing the developer's C code to be compiled for a specific implementation by generating a compiler using Altera's Quartus design tools. This can provide faster performance and higher responsiveness for industrial interfaces, while reducing code size and memory requirements, reducing equipment costs.

LatTIce Semiconductor's LFE2-50E LCD-Pro Graphics Evaluation Kit evaluates a flexible, configurable set of IP cores for versatile and powerful display control, graphics and video applications with 7-inch TFT screens. Based on the industry standard AMBA bus architecture, the library allows the LCD-Pro IP to interconnect with various AMBA bus compatible system components such as ARM processors.

The LCD-Pro IP core is optimized for LatTIce FPGAs and is specifically optimized for the LatTIceECP2 low-cost FPGA family. The library contains multiple IP cores capable of controlling a wide range of flat panel displays from low-end CIF and QVGA to high-definition TFT in 8, 16 or 24-bit color and using over 30 commercially available displays in the field. The IP supports multi-layer image compositing available in display controllers, supporting simple overlays, color-keyed transparency, alpha blending and alpha masking, and variable layer color depth, size, positioning, and smooth scrolling.

Figure: Lattice LCD-Pro IP core.

This kit can be used to build video modules, handle various formats and combine graphics to build clear and usable human-machine interfaces in industrial applications. All of these provide a powerful set of technologies for developing the latest industrial interfaces. From dedicated hardware to software-configurable devices, these devices enhance the designer's ability to control displays and provide the best human-machine interface.

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