The pursuit of storage density to reduce the cost of storage continues to promote the development of NAND flash memory technology. NAND flash memory technology has evolved rapidly from the original SLC era, across MLC and TLC to the QLC era, and has comprehensively switched from the original 2D plane technology to 3D stacking technology. And 3D NAND flash memory technology has also developed from the original 32-layer stack to the latest generation of 128 layer stack.
With the increasing storage density of NAND, the design of ECC of SSD main control chip is facing a great challenge. On the one hand, with the increase of NAND storage density and the serious deterioration of data reliability of flash memory, the ECC technology of SSD main control chip has also completed the overall migration from the original BCH technology to the advanced LDPC error correction technology. Especially after entering the era of QLC, NAND flash storage medium needs SSD master chip to further provide higher error bit correction capability. On the other hand, the design complexity of the advanced LDPC error correction technology with high error correction capability is high, which brings about a sharp rise in the power consumption of the main control chip and a great hidden danger to the stability of the SSD system. Moreover, the complex decoding process of LDPC, especially soft decoding, will occupy a large amount of flash data bandwidth, which will reduce the actual use performance of SSD users, and seriously deteriorate the data read-write delay, resulting in a very poor user experience. Therefore, in order to adapt to the development of NAND flash memory technology, the research of ECC error correction technology has always been one of the core competitiveness of SSD master chip manufacturers.
Figure 1: 4K LDPC greatly extends NAND service life
Lianyun’s agile ECC technology is based on the advanced ECC NAND flash signal processing technology, which can greatly improve the reliability of flash data and greatly extend the life of SSD. Recently, Lianyun technology has made a second technological innovation on the basis of agile ecc2 technology based on 2K LDPC error correction, and successfully realized the development and verification of the third generation agile ecc3 flash signal processing technology based on 4K LDPC error correction. According to the senior management of Lianyun technology, the new generation of SSD main control chip to be launched by Lianyun technology will fully enable 4K LDPC error correction technology, which is the first time that domestic SSD main control chip manufacturers have achieved a continuous breakthrough in this technology. From the initial technology to the transformation of technology transcendence, it will surely lead the technological innovation and development of SSD main control chip, and 4K in the future LDPC error correction technology will become the essential key technology of SSD master chip.
Compared with 2K LDPC error correction technology, 4K LDPC error correction performance has a significant improvement both in hard decoding and soft decoding. Compared with 2K LDPC, the error correction failure probability (Ufer) of 4K LDPC can be reduced by at least two orders of magnitude at the same original bit error rate (rber). In other words, under the same Ufer requirement, 4K LDPC can tolerate higher rber of flash memory particles, which can greatly extend the service life of flash memory.
Figure 2: 4K LDPC and 2K LDPC decoding capability improvement
Lianyun’s agile ecc3 technology introduces 4K LDPC, which greatly improves both the hard decoding ability and the soft decoding ability compared with 2K LDPC. The improvement of LDPC’s soft decoding ability ensures the reliability of flash data in the worst case and greatly extends the service life of SSD; while the improvement of LDPC’s hard decoding ability can greatly reduce the probability of entering LDPC’s soft decoding, thus avoiding the complex LDPC’s soft decoding process and greatly improving the user’s actual use experience. In principle, the length of LDPC code from 2K to 4K will increase the complexity of circuit implementation, increase the chip power consumption and cost. But Lianyun technology 4K LDPC error correction technology adopts unique LDPC codec architecture and advanced dynamic power management technology, which greatly optimizes the system power consumption and cost. Lianyun’s third-generation agile ECC technology based on 4K LDPC has undergone a series of technological innovations, which not only greatly improves the flash error correction capability of the main control chip, but also optimizes the chip power consumption, bringing excellent performance and ultra-low power consumption experience to users.
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