Introduction to FPGA: Construction of functional simulation platform for the first engineering example
This article is excerpted from the book “FPGA / CPLD learning while practicing – quick start Verilog / VHDL” by privileged students
For the code in the book, please visit the online disk:
After simply adding some theoretical knowledge, let’s take the current example project as an example to establish a simulation environment. Of course, the ultimate protagonist of this simulation environment is Modelsim (alternate Modelsim), but before that, we still need to sort out the various interfaces required by Modelsim and the relationship between relevant documents.
Back to our Quartus II tool, in the previous project creation wizard, we have actually set the simulation tool as Modelsim Altera, but we still need to make more detailed configuration. First, we can click processing à start à start test bench template writer in the menu bar, and then the prompt “test bench template writer was successful” pops up. Then we have created a Verilog test script. In this script, we can design some test incentive inputs and observe the corresponding outputs, so that we can verify whether the design code of the original project meets the requirements.
As shown in the figure, we can open the next folder named / simula.0/simula.5 VT’s test script file was created.
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Figure 5.29 test script file
We can open this file in Quartus II and edit it again, as shown in Figure 5.30.
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Figure 5.30 test script code
★ code explanation
L27: timescale is used to declare the unit and accuracy of simulation time. 1ns before “/” indicates the basic unit of time, and 1ps after “/” indicates the simulation progress. See the explanation of L46 for application examples.
L28 / l59: declare the module. The module name is ex0_ vlg_ TST, different from RTL level design, there is no need to list the names of input and output signals here.
L46: “#1000” indicates that the simulation time has passed 1000ns. If it is written as “999.999”, it means that the simulation time has passed 999.999ns, accurate to PS, that is, 3 decimal places here.
L30 / L31: signal declaration of two keys. The input signal of the design file is actually the output signal of the test script, so it is reg type. It can be assigned in the test script.
In fact, the signal of L33: wire is the signal of LED output. It cannot be assigned in the test script.
L36-41: an example declaration of the design file (the object to be tested), which is mainly to export its interface to the test script file.
L43-57: write a sequential key value simulation assignment program. Output different combined values to two key signals every 1000ns.
In the test script, through the key_ Left and key_ Right the different values of the two excitation signals, we can observe the LED_ The change of light signal to verify whether the original design code meets the design requirements.
After completing the test script writing, we need to open the assign à settings option in the menu bar, select category à EDA tool setting à simulation, and make the settings shown in Figure 5.31 in the relevant attributes on the right. After selecting complex test bench, we need to click the following testbenches… Button to select the test script just created.
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Figure 5.31 simulation setup window
As shown in Figure 5.32, first pop up the test benches window above, then click the new… Button, and then pop up the following window. In this window, we enter the names of test bench name and top level module in test bench according to the actual situation, then select the test script file under test bench and simulation files, and then add to the lowest list. Click OK after completion, as shown in Figure 5.33, we can see the relevant information of the test script just added appears in the list of test benches window, and then click OK to complete the setting.
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Figure 5.32 test script settings