Due to the frequent occurrence of Axi protocol in zynq architecture and common interface IP cores, the explanation timing of Xilinx’s protocol manual is relatively scattered. Therefore, the author collects several timing of Axi protocol for convenient programming.

1》AXI_ Lite protocol:

(1) Read address channel, including arvalid, araddr and arready signals;

(2) Read data channel, including rvalid, rdata, rready and rresp signals;

(3) Write address channel, including awvalid, awaddr and awready signals;

(4) Write data channel, including wvalid, wdata, wstrb, wready signals;

(5) Write response channel, including bvalid, bresp and ready signals( 6) System channel, including aclk and aresetn signals.

The signals of axi4 bus and axi4 Lite bus also have its naming characteristics: the read address signals start with AR (A: address; R: Read) write address signals start with aw (A: address; W: Write) read data signals start with R (R: read) write data signals start with w (W: write)

The signals of Xi4 bus and axi4 Lite bus also have its naming characteristics: the read address signals start with AR (A: address; R: Read) write address signals start with aw (A: address; W: Write) read data signals start with R (R: read) write data signals start with w (W: write)

The signals of axi4 bus and axi4 Lite bus also have its naming characteristics: the read address signals start with AR (A: address; R: Read) write address signals start with aw (A: address; W: Write) read data signals start with R (R: read) write data signals start with w (W: write)

The signals of axi4 bus and axi4 Lite bus also have its naming characteristics: the read address signals start with AR (A: address; R: Read) write address signals start with aw (A: address; W: Write) read data signals start with R (R: read) write data signals start with w (W: write)

The signals of axi4 bus and axi4 Lite bus also have its naming characteristics: the read address signals start with AR (A: address; R: Read) write address signals start with aw (A: address; W: Write) read data signals start with R (R: read) write data signals start with w (W: write)

AXI_ Lite read timing:

Introduction of several timing of Axi bus protocol

AXI_ Lite: write timing

Introduction of several timing of Axi bus protocol

2》AXI_STREAM:

Axi4 stream bus consists of:

(1) Aclk signal: bus clock, rising edge valid;

(2) Aresetn signal: bus reset, active at low level

(3) Tread signal: the slave tells the host to be ready for transmission;

(4) Tdata signal: data, optional width 32, 64128256bit

(5) Tstrb signal: each bit corresponds to an effective byte of Tdata, and the width is Tdata / 8

(6) Tlast signal: the master tells the slave that this transmission is the end of burst transmission;

(7) Tvalid signal: the host tells the slave that the data transmission is valid;

(8) Tuser signal: user-defined signal with a width of 128bit.

Introduction of several timing of Axi bus protocol

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