1 Preface

The circuit industry has become the key to the development of national economy, and IC design, manufacturing, packaging and testing are the three pillars of the development of IC industry. This is the consensus of leaders at all levels and the industry. Microelectronic packaging not only directly affects the electrical performance, mechanical performance, optical performance and thermal performance of the integrated circuit itself, but also affects its reliability and cost. To a large extent, it also determines the miniaturization, multi-function, reliability and cost of the whole electronic system. Microelectronic packaging has been paid more and more attention, and is in a vigorous development stage at home and abroad. This paper attempts to summarize the new microelectronic packaging technologies which have been developing rapidly since 1990s, including solder ball array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D) and system packaging (SIP). Their development and technical characteristics are introduced. At the same time, the concept of three-stage package for microelectronics is described. Some thoughts and suggestions on the development of new microelectronic packaging technology in China are put forward. This paper attempts to summarize the new microelectronic packaging technologies which have been developing rapidly since 1990s, including solder ball array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP), three-dimensional packaging (3D) and system packaging (SIP). Their development and technical characteristics are introduced. At the same time, the concept of three-stage package for microelectronics is described.

Introduction of new microelectronic packaging technology in China

2 microelectronic three stage package

First of all, we will describe the concept of three-stage packaging. Generally speaking, microelectronic packaging is divided into three levels. The so-called primary packaging is to package one or more integrated circuit chips with appropriate packaging forms after the semiconductor wafer is cracked, and connect the chip’s solder area with the external pins of the package by wire bonding (WB), tape automatic bonding (TAB) and flip chip bonding (FCB), so as to make them become electronic components or assemblies with practical functions. Primary packaging includes single chip module (SCM) and multi chip module (MCM). The three-level packaging is to connect the two-level packaging products with the motherboard through layer selection, interconnection socket or flexible circuit board to form a three-dimensional packaging and form a complete system. This level packaging should include connector, laminated assembly, flexible circuit board and other related materials, design and assembly technology. This level is also called system level encapsulation. The so-called microelectronic package is a whole concept, including all the technical contents from one pole package to three pole package. We should put the current understanding into the track of International Microelectronic Packaging, which is not only conducive to the technical exchange between China’s microelectronic packaging industry and foreign countries, but also conducive to the development of China’s microelectronic packaging itself.

3 new microelectronic packaging technology

The history of IC packaging can be divided into three stages. The first stage, before the 1970s, was mainly plug in packaging. It includes the original metal round (to type) package, the later ceramic dual in-line package (cdip), ceramic glass dual in-line package (cerdip) and plastic dual in-line package (PDIP). PDIP, in particular, has become a mainstream product due to its excellent performance, low cost and mass production. In the second stage, after the 1980s, surface mounted Quad lead packages were mainly used. At that time, surface mount technology was known as a revolution in the field of electronic packaging and developed rapidly. Accordingly, a number of packaging forms suitable for surface mounting technology, such as PLCC, PQFP, PSOP and nlfp, emerged and developed rapidly. Because of high density, small lead pitch, low cost and suitable for surface mounting, PQFP became the leading product in this period. The third stage, after the 1990s, is mainly in the form of surface array packaging. Mcm-d, mcm-l and MCM-C / d.

3.13d package

There are three main types of 3D packaging, namely embedded 3D packaging. At present, there are three main ways: one is to “embed” R, C or IC components in various substrates or multi-layer wiring dielectric layers, and then mount SMC and SMD on the top layer to realize three-dimensional packaging. This structure is called embedded 3D packaging; The second is to implement multi-layer wiring on the active substrate after wafer scale integration (WSL), and then mount SMC and SMD on the top layer to form a three-dimensional package. This structure is called active substrate 3D package; The third is based on the 2D package, the multiple bare chips, package chips, multi chip modules and even wafers are stacked and interconnected to form a three-dimensional package. This structure is called stacked 3D package. In these types of 3D packaging, the most rapid development is stacked bare chip packaging. There are two reasons. One is driven by the huge market of mobile phones and other consumer products, which requires to reduce the package thickness while increasing the functions. The second is that the process is basically compatible with the traditional process. After improvement, it can be mass produced and put into the market soon. According to prismarks, the world’s mobile phone sales will increase from 393m in 2001 to 785m-1140m in 2006. The annual growth rate is 15-24%. Therefore, it is estimated that the growth rate of stacked bare chip packaging will be 50-60% from now to 2006. Fig. 6 shows the outline of a stacked bare chip package. Its current level and development trend are shown in Table 3.

There are two ways to stack bare chip. One is pyramid style. From bottom to top, the size of bare chip becomes smaller and smaller; The other is the cantilever type, and the stacked chips are the same size. At the beginning of its application in mobile phones, stack bare chip packaging was mainly used to stack flash memory and SRAM together. At present, flash memory, DRAM, logic IC and analog IC can be stacked together. The key technologies involved in stack bare chip packaging are as follows. ① Wafer thinning technology, due to the requirements of mobile phones and other products packaging thickness is getting thinner, the current packaging thickness is required to be less than 1.2mm or even 1.0mm. The number of stacked chips is increasing, so the chip must be thinned. Wafer thinning methods include mechanical grinding, chemical etching or ADP (atmosphere downstream plasma). Mechanical grinding thinning is generally 150 μ M. However, it can reach 100% by plasma etching μ m. For 75-50 μ M thinning is under development; ② Low arc bonding, because the chip thickness is less than 150 μ m. Therefore, the bonding radian must be less than 150 μ m。 Currently 25 μ The normal bonding arc height of M gold wire is 125 μ m. However, 75% can be achieved by using reverse wire bonding μ The arc height below M. At the same time, the reverse wire bonding technology needs to add a bending process to ensure the gap of different bonding layers; ③ For wire bonding technology on cantilever, the longer the cantilever is, the larger the deformation of the chip is; ④ Wafer bump manufacturing technology; ⑤ No swing molding technology for bonding wire. Due to the higher density, longer length and more complex shape of bonding wires, the possibility of short circuit is increased. Using low viscosity molding compound and reducing the transfer speed of molding compound can help to reduce the swing of bonding wire. At present, no swing molding technology has been invented.

3.2 solder ball array package (BGA)

Array package (BGA) is a new package developed in the early 1990s.

The I / O terminals of BGA package are distributed under the package in the form of round or columnar solder joints. The advantage of BGA technology is that although the number of I / O pins increases, the pin spacing increases instead of decreasing, thus improving the assembly yield; Although its power consumption increases, BGA can be soldered by controlled collapse chip method, which can improve its electrothermal performance; The thickness and weight are reduced compared with the previous packaging technology; The parasitic parameters are reduced, the signal transmission delay is small, and the use frequency is greatly improved; Coplanar welding can be used for assembly with high reliability.

The outstanding advantages of this BGA are as follows: 1) better electrical performance: BGA uses solder ball instead of lead, short lead out path, reducing pin delay, resistance, capacitance and inductance; ② Higher packaging density; Because the solder balls are arranged in the whole plane, the number of pins is higher for the same area. For example, the BGA with 31 mm side length has 900 pins when the pitch of solder ball is 1 mm, compared with 208 pins for QFP with 32 mm side length and 0.5 mm pitch; ③ The pitch of BGA is 1.5mm, 1.27mm, 1.0mm, 0.8mm, 0.65mm and 0.5mm, which is completely compatible with the existing surface mounting technology and equipment, and the installation is more reliable; ④ Due to the self-aligning effect of surface tension during solder melting, the deformation loss of traditional packaging leads is avoided, and the assembly yield is greatly improved; ⑤ BGA pin is firm and easy to transport; ⑥ Solder ball lead out is also suitable for multi chip module and system packaging. Therefore, BGA has got explosive development. Due to the different substrate materials, BGA includes PBGA, CBGA, TBGA, EBGA, MBGA and FCBGA. PQFP can be used for surface mounting, which is its main advantage. However, when the lead pitch of PQFP reaches 0.5mm, the complexity of its assembly technology will increase. In the applications where the number of leads is more than 200 and the package size is more than 28mm square, it is inevitable for BGA package to replace PQFP. Among the above BGA packages, FCBGA is the most promising one to become the fastest growing BGA package. We might as well take it as an example to describe the BGA process technology and materials. In addition to all the advantages of BGA, FCBGA also has the following advantages: 1) excellent thermal performance, the back of the chip can be installed with a radiator; ② The FCBGA has high reliability. The anti fatigue life of FCBGA is greatly enhanced due to the effect of the filler under the chip; ③ Strong repairability.

Because other components have been installed on the surface assembly board, the BGA special small template must be used. The template thickness and opening size should be determined according to the ball diameter and ball distance. After printing, the printing quality must be checked. If it is unqualified, the PCB must be cleaned and dried before re printing. For CSP with ball pitch less than 0.4mm, solder paste can not be printed, so it is not necessary to process the repair template, and directly brush paste flux on the PCB pad. Put the PCB that needs to be removed into the welding furnace, press the reflow key, wait for the machine to finish according to the set program, press the in and out key when the temperature is the highest, use the vacuum suction pen to remove the components to be removed, and then cool the PCB.

The key technologies involved in FCBGA include chip bump manufacturing technology, flip chip soldering technology, multilayer PCB manufacturing technology (including multilayer ceramic substrate and BT resin substrate), chip underfill technology, solder ball attachment technology, heat sink attachment technology, etc. It involves packaging materials mainly include the following categories. Bump materials: Au, PbSn and AuSn, etc; Under bump metallization materials: Al / NIV / Cu, Ti / Ni / Cu or Ti / w / Au; Welding materials: PbSn solder, lead-free solder; Multilayer substrate materials: high temperature co fired ceramic substrate (HTCC), low temperature co fired ceramic substrate (LTCC), BT resin substrate; Underfill material: liquid resin; Heat conductive adhesive: silicone resin; Heat sink: copper.

3.3 chip size package (CSP)

CSP (chip scale package) package means chip level package. CSP is the latest generation of memory chip packaging technology, and its technical performance has been improved. CSP package CSP package can make the ratio of chip area to package area exceed 1:1.14, which is quite close to the ideal situation of 1:1. The absolute size is only 32 square mm, which is about 1 / 3 of the common BGA and only 1 / 6 of the TSOP memory chip area. Compared with BGA package, CSP package can increase storage capacity three times in the same space.

Chip size package (CSP) and BGA are products of the same era, which is the result of miniaturization and portability. The definition of CSP given by American JEDEC is: the package whose LSI chip package area is less than or equal to 120% of LSI chip area is called CSP. Since many CSPs adopt the form of BGA, in the past two years, the authoritative people in the packaging industry believe that BGA is the one with solder ball pitch greater than or equal to LMM, and CSP is the one with solder ball pitch less than LMM. Because CSP has more outstanding advantages: 1) ultra small package with approximate chip size; ② Protect the bare chip; ③ Excellent electrical and thermal properties; ④ High packaging density; ⑤ Easy to test and aging; ⑥ Easy to weld, install, repair and replace. As a result, the mid-1990s witnessed a large-span development, with an annual growth of about double. As CSP is in the stage of vigorous development, its types are limited. Such as rigid substrate CSP, flexible substrate CSP, lead frame CSP, micro molding CSP, solder joint array CSP, micro BGA, bump chip carrier (BCC), QFN CSP, chip stack CSP and wafer level CSP (WLCSP). Generally, the pitch of CSP is less than 1.0 mm, including 1.0 mm, 0.8 mm, 0.65 mm, 0.5 mm, 0.4 mm, 0.3 mm and 0.25 mm. Table 2 shows the CSP series.

Generally, CSP is to cut the wafer into a single IC chip and then implement the post packaging, while WLCSP is different. All or most of the process steps are completed on the silicon wafer that has completed the previous process, and finally the wafer is directly cut into separate independent devices. So this kind of package is also called wafer level package (WLP). Therefore, in addition to the common advantages of CSP, it also has unique advantages: 1) high efficiency of packaging processing, multiple wafers can be processed at the same time; ② It is light, thin, short and small; ③ Compared with the previous process, only two processes of RDL and bump making are added, and the rest are all traditional processes; ④ It reduces multiple tests in traditional packaging. Therefore, many large IC packaging companies in the world have invested in the research, development and production of this kind of WLCSP. The disadvantages of WLCSP are the low number of pins, lack of standardization and high cost.

The central pin form of CSP packaging memory chip effectively shortens the signal conduction distance, and its attenuation decreases. The chip’s anti-interference and anti noise performance can also be greatly improved, which also makes the access time of CSP improve 15% – 20% compared with BGA. In CSP packaging, memory particles are soldered on the PCB board by solder balls. Because of the large contact area between solder joints and PCB board, the heat generated by memory chips in operation can be easily transmitted to the PCB board and emitted. CSP package can dissipate heat from the back with good thermal efficiency. The thermal resistance of CSP is 35 ℃ / W, while that of TSOP is 40 ℃ / W.

CSP technology is put forward in the upgrading of electronic products, its purpose is to use large chips (more functions, better performance, more complex chips) to replace the previous small chips, its package occupies the same or smaller area of the printed board. It is precisely because of the small and thin package of CSP products that CSP products are rapidly applied in handheld mobile electronic devices. In August 1996, sharp began to mass produce CSP products; In September 1996, Sony began to assemble cameras with CSP products provided by Ti and NEC; In 1997, the United States also began to produce CSP products. There are dozens of Companies in the world that can provide CSP products, and there are more than 100 kinds of CSP products

The key technologies involved in WLCSP include not only the metal deposition technology, lithography technology and etching technology, but also the rewiring (RDL) technology and bump manufacturing technology. In order to adapt WLP to the wide pad pitch of SMT two-stage package, it is necessary to redistribute these pads, so that these pads are arranged on the active surface of the chip instead of around the chip. Solder bumps can be made by electroplating, electroless plating, evaporation, ball placement and solder paste printing. At present, electroplating is still the most widely used method, followed by solder paste printing. The material of UBM in rewiring is Al / NIV / Cu, T1 / Cu / Ni or Ti / w / Au. The dielectric materials used are photosensitive BCB (benzocyclobutene) or PI (polyimide). The bump materials include Au, PbSn, AuSn, in and so on.

3.4 system encapsulation (SIP)

There are usually two ways to realize the function of electronic whole machine system. One is system on chip (SOC). That is to realize the function of the whole electronic system on a single chip; The other is system in package (SIP). The function of the whole system is realized by encapsulation. Academically speaking, these are two technical routes, just like monolithic integrated circuits and hybrid integrated circuits, each with its own advantages and application market. The author thinks that SOC should be mainly used for high performance products with long application cycle, while SIP is mainly used for consumer products with short application cycle.

An important feature of SIP is that it does not define the type of session to be established, but only defines how the session should be managed. With this flexibility, SIP can be used in many applications and services, including interactive games, music and video on demand, as well as voice, video and web conferencing. SIP messages are text-based and therefore easy to read and debug. The programming of the new service is simpler and more intuitive for designers. SIP reuses MIME type descriptions just like e-mail clients, so session related applications can start automatically. SIP reuses several mature Internet services and protocols, such as DNS, RTP, RSVP, etc.

SIP is flexible, extensible and open. It stimulates the power of Internet and fixed and mobile IP network to launch new generation services. SIP can complete network messages on multiple PCs and telephones, and simulate Internet session.

SIP uses mature assembly and interconnection technology to integrate various integrated circuits, such as CMOS circuits, GaAs circuits, SiGe circuits or optoelectronic devices, MEMS devices and various passive components, such as capacitors and inductors, into a package to realize the functions of the whole system. The main advantages include: 1) using the existing commercial components, the manufacturing cost is low; ② The period of products entering the market is short; ③ Regardless of the design and process, it has great flexibility; ④ It is relatively easy to integrate different types of circuits and components. Slim (single integrated module) developed by PRC of Georgia Institute of technology is a typical representative of SIP. After the completion of the project, the packaging efficiency, performance and reliability will be increased by 10 times, and the size and cost will be greatly reduced. The target to be achieved by 2010 includes wiring density of 6000cm / cm2; The heat density reaches 100W / cm2; The density of the element reaches 5000 / cm2; The I / O density reaches 3000 / cm2.

Although SIP is still a new technology, which is not mature at present, it is still a promising technology, especially in China, which may be a shortcut to develop the whole system.

4. Thinking and suggestions

In the face of the rapid development of microelectronic packaging in the world, we must think deeply about some problems when analyzing the current situation in China.

1、 We attach great importance to the vertical integration of microelectronic three-stage package. We should take the electronic system as the leader, and involve the first level, second level and third level packaging, so as to occupy the market, improve the economic efficiency and develop continuously. We have proposed that mobile phones and radars should be used as technology platforms to develop microelectronic packaging in our country, just for this reason.

2、 Attach great importance to the cross and integration of different fields and technologies. The cross and fusion of different materials produce new materials; Different technologies cross and merge to produce new technologies; The intersection and integration of different fields produce new fields. In the past, there were a lot of exchanges with the same industry, but not enough exchanges with different industries. We should give full play to the role of each branch of the electronic society and actively organize such technical exchanges.

3、 Microelectronic packaging and electronic products are inseparable. It has become the core technology restricting the development of electronic products and even systems. It is one of the advanced manufacturing technologies in the electronic industry. Whoever has mastered it will grasp the future of electronic products and systems.

4、 Microelectronic packaging must keep pace with the times to develop. The history of International Microelectronic Packaging has proved this point. How can microelectronic packaging keep pace with the times in China? The most urgent task is to study the development strategy of microelectronic packaging in China and formulate the development plan. The second is to optimize the research and production system of microelectronic packaging in China. Third, actively advocate and vigorously develop the original technology that belongs to China’s independent intellectual property rights. Otherwise, we will be more and more backward. In this regard, we can learn from the experience of South Korea and Taiwan.

Five, our concept, technology and management must be in line with international standards and take the road of international cooperation to integrate the essence of our nation with the wonderful world and develop together.

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