In electronic technology, N / 2 (n is odd) frequency division circuit has an important application. For a specific input frequency, it needs n / 2 frequency division to get the required output, which requires the circuit to have n / 2 non integer multiple frequency division function. CD4013 is a double-D flip-flop. On the basis of several two-way frequency dividing circuits mainly composed of CD4013 and feedback control such as XOR gate, N / 2 frequency dividing circuit can be easily formed.
CD4013 consists of two identical and independent data triggers. Each trigger has independent data, set, reset, clock input and Q and Q output. This device can be used as a shift register and can be used as a counter and trigger by connecting the Q output to the data input. When the rising edge of the clock is triggered, the logic level added to the D input is transmitted to the Q output. Set and reset are independent of the clock, and are performed by the high level on the set or reset line respectively.
This article is to introduce the double-D trigger of CD4013 in detail, so that you can have a more comprehensive understanding of CD4013.
Introduction of double D flip flop of CD4013
4013 double D flip flop structure function principle application circuit
After VD1 ~ VD4 rectification, R1 current limiting, C1 filtering and vs voltage stabilizing, AC 220 V voltage provides + 12 V working voltage for optical control circuit and executive circuit.
In the daytime, Rg1 and Rg2 are in low resistance state due to light irradiation. S1 end of IC is in low level, R1 end is in high level, 1 end outputs low level, VT is in cut-off state, K is in release state, and el is not on.
At night, Rg1 and Rg2 turn to high level at S1 end, low level at R1 end, high level at Q1 end, VT is saturated, K is electrified, its normally open contact is connected, and el is on.
After daybreak, the resistance of Rg1 and Rg2 decreases, the Q1 end of IC outputs low level again, VT is cut off, K is released and el is off. 4013 is an integrated flip-flop chip with two independent D flip flops. Each flip-flop has a set terminal, a reset terminal, a clock terminal, a data input terminal, two output terminals Q and Q / terminals.
Voltage range: 3-18v
When R is 1 and S is 0, regardless of the state of D and Cl (clock), the output Q must be 0, so r can be called the reset end. When s is 1 and R is 0, the output Q must be 1, and S is called the set end.
When R and s are both 0, Q acts when there is a rising edge of pulse at CP end, specifically q = D, that is, if D is 1, then q is 1, if D is 0, then q is 0.
Press S1, r = 1, circuit reset, Q end output 0, press S2, s = 1, circuit set, Q end output 1. When it is 1, the triode is on, and the relay is powered on. After S2 is pressed, the relay always keeps the state of suction and release, only when S1 is pressed. This circuit is a basic RS trigger.
When S1 is not pressed, the reset end r = O, otherwise if r = L, the circuit will forcibly reset q = 0, and the charged charge will discharge to the Q end through R2, and finally make r = 0, which is the steady state of the circuit. When S1 is pressed once, the potential of CP terminal changes from “O” to “1”, and its rising edge triggers the circuit to transmit the data of D terminal. Since d = 1, q = 1, which is a transient state. When the voltage at both ends of C reaches the reset level, r = 1, the circuit is reset, and the Q end becomes low level? The transient steady state ends and the circuit returns to steady state. The above figure is the corridor lamp delayed turn off circuit. In steady state, the Q end is low, the triode is off, the relay does not work, and the bulb does not light. When you press S1, the circuit enters the transient steady state. Q = 1, the triode is saturated, the relay is powered on, its normally open contact is closed, and the ladder lamp is turned on. After the transient steady state, the lamp automatically goes out. The transient steady-state time is the time when the bulb lights up, which is determined by the parameters of R2 and C.
When the voltage of C2 end rises to the reset level, the Q end becomes low, and C2 passes through VD2
Discharge to Q terminal when Q terminal is at low level, because Q / is the inverted phase output terminal of Q, q is at high level, and the high level charges C1 through RP1. When C1 terminal voltage rises to set level, Q becomes high level, Q becomes low level, high level of Q terminal charges C2, low level of Q terminal makes C1 discharge to it, so cycle in Q terminal High and low levels appear alternately at the q-terminal, forming oscillation. Because the output Q and Q of the circuit do not have a stable state, the circuit is called astable oscillator: the oscillation signal at the Q end is added to the base of the triode to amplify, which drives the loudspeaker to emit a loud audio call: the oscillation frequency is determined by rp1.rp2.c1 and C2, so it is also called audio signal generator.