In the aviation field, 1553B bus and ARINC429 Bus are two widely used bus standards. 1553B bus is widely used in aircraft avionics system, while ARINC429 Bus is widely used in airborne weapon system. As the communication and control intermediary between weapon system and avionics system, the launcher needs to convert the data between the two bus standards. Now two kinds of bus data formats are briefly introduced.
1) Brief introduction of gjb1553b bus
The gjb1553b data bus adopts Manchester encoding and decoding protocol, which performs data transmission in asynchronous, command / response mode. It usually adopts half duplex mode, and its transmission rate is 1mbit / s. Manchester code is different from common non return to zero (NRZ) code. In the circuit, the “0” of NRZ code is represented by low level; The “0” of Manchester code is represented by the level jump from low to high. Similarly, “1” of NRZ code is represented by high level; The “1” of Manchester code is represented by the level jump from high to low. In practical application, differential Manchester code is used. The waveform comparison between differential Manchester code and non return to zero (NRZ) is shown in Figure 1.
2) Introduction to ARINC 429
ARINC429 Bus is one of the most widely used airborne aviation buses at present. It is a one-way broadcast bus, and its information transmission rate is 12.5 ~ 100kbit / s . ARINC429 stipulates that the data transmission adopts bipolar return to zero code (as shown in Figure 2), that is, the modulation signal is composed of “high”, “zero” and “low” states, and the transmission medium is twisted shielded cable.
Hardware design of conversion circuit based on FPGA
The core work of data conversion is to encode and decode the data of various bus standards. In the traditional data conversion circuit, the data is encoded and decoded by professional editing chips of various bus standards, and then processed. The traditional conversion circuit design is relatively simple, but the power consumption is high, and the programmable logic resources are not fully utilized. This paper introduces a design of data conversion circuit based on FPGA.
Data conversion hardware circuit design:
The data conversion circuit mainly includes FPGA, DSP and peripheral driver conditioning circuit. DSP controls the timing of each module, FPGA is responsible for encoding and decoding of Manchester code, DSP peripheral control logic, data format conversion, clock signal generation and data storage, and the data is stored in high-speed and low-power CMOS static RAM. The hardware design block diagram of data conversion circuit is shown in Figure 3.
Considering the data communication between the circuit modules, the data line needs to occupy a large area of PCB space, and crosstalk may occur between high-speed signals. So here we integrate the encoding and decoding part of 1553B chip into FPGA, and adjust the data level to the range suitable for FPGA reception through mode transformer and simple shaping circuit. This can reduce the power consumption of the whole data conversion circuit, improve the integration of CPU control board, reduce the heat, simplify the PCB wiring, and improve the stability of the whole system.
2 system simulation verification
The whole FPGA function module is integrated by Verilog language, and the key signals and modules in the design are simulated by FPGA simulation tools, which can greatly save development time, improve the stability of system operation, and reduce the development cost.
1) Implementation of gjb1533b data conversion
The data of GJB1553B is encoded by Manchester code. In order to realize the data conversion, the Manchester code must be decoded. The identification of synchronization header is very important. If it can not be identified correctly, the command may be lost or the parameter setting may be wrong. The technology we adopt here is: the clock of data sampling logic circuit monitors the data input line, and takes the level jump on the data input line as a trigger event. Whether the trigger event is valid or not depends on the following conditions:
If there are 1.5 bits of low level and two valid Manchester code bits in the data queue collected later, the command word synchronization header is considered valid; If there are 1.5 bits of high level and two valid Manchester code bits in the data queue collected later, the data word synchronization header is considered valid. After receiving 17 bit Manchester code successively, the last bit is odd check bit. If the odd check bit is correct, a correct and complete word is received. Whether the 16 bit word is command word or data word is determined by the format of synchronization header.
The simulation is carried out in FPGA, and the waveform is shown in Figure 4.
It can be seen from the figure that the Manchester code in the FPGA has successfully converted the general binary data of the computer.
2) Realization of ARINC429 data conversion
The basic information unit of ARINC429 data is a data word composed of 32 bits. Each data word is divided into five groups: the first to eighth bits are label bits, the ninth to tenth bits are source / destination identification bits, the eleventh to 29th bits are data area, the 30th to 31st bits are symbol bits, and the 32nd bits are parity bits. In fact, the use of data bits in ARINC429 can be defined by the system designer to a great extent. Under the basic characteristics of 32 bit serial transmission, as long as both the sender and the receiver use the same protocol. According to 429 data format, the encoding and decoding format is integrated in FPGA with Verilog language, and the simulation waveform is shown in Figure 5.
It can be seen from the figure that ARINC429 data in FPGA has been successfully converted into general binary data of computer.
Through the simulation, we can see that gjb1553b and ARINC429 are converted into binary data accurately and stably after decoding by their respective encoding and decoding modules in FPGA. Due to the strong portability of Verilog language, the encoding and decoding module can be directly transplanted to other modules to achieve the communication transmission of two kinds of bus data.