1. Time ruler: Format: ` timescale simulation time unit / time precision. For example: ` timescale 1ns / 100ps, simulation time unit bit 1ns, but simulation time accuracy can reach 100ps.

You should notice that there is a symbol, which means to delay the corresponding time unit. The time unit is determined by the timescale. Generally, the time unit and simulation precision are defined at the beginning of testbench, such as’ timescale 1ns / 1ps’. The first one represents the time unit, and the latter one represents the simulation time precision. In the above example, a clock cycle is 20 units, that is, 20 ns. The concept of simulation time precision is that you can see the corresponding signal value at 1.001ns, but if the scale is 1ns / 1ns, the value at 1.001ns cannot be seen.

2. Define signal type: the input signal in the original module is defined as reg type, and the output signal in the original module is defined as wire type. But there is a problem here. If there is a need for a module in testbench itself, such as to generate a clock and send it to the module to be simulated, how to define the signal type?

In fact, it is the same definition. The input signal is defined as reg type and the output is defined as wire type. However, the output of this module is sent to the simulation module for input. This input is wire type, as shown in the CLK below_ D1 and CLK_ D2 these two signals can only be defined as wire type.

Introduce the writing skills of testbench in FPGA

3. Sometimes, a large number of data input is required for the input test data of the file, and the direct assignment is cumbersome. You can generate the data, read the data into the register, and take it out when necessary. Use the $readmemb system task to read binary vectors from text files and $readmemh to read hex files. For example: reg [7:0] MEM [0:255] / / an 8-bit-wide, 256 long register group initial $readmemh (“E: / readhex/ mem.dat “, MEM) / / read the. Dat file into the register group MEM, initial $readmemh (” E: / readhex/ mem.dat “, MEM, 128, 1) / / parameter is the address start and end of register loading data.

4. Write the simulation results to the file. Use the function $fwrite ($fddisplay) and the function function to write the data to the txt file (opposite to fscanf). The difference between $fwrite and $fdisplay is that if $fwrite writes a number, it will not automatically change the line. You can add \ n to change the line, and $fdisplay will automatically change the line. Only $fwrite is introduced here, and $fddisplay is basically the same as $fwrite.

         

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