Author: George Diniz, product line manager, ADI company

Abstract

abstract

The JESD204A/JESD204B industry standard for serial interfaces was developed to address the problem of interconnecTIng the newest wideband data converters with other system ICs in an efficient and cost saving manner. The moTIvaTIon was to standardize an interface that would reduce the number of digital inputs/outputs between data converters and other devices, such as field programmable gate arrays (FGPAs) and system on a chip (SoC) devices through the use of a scalable high speed serial interface.

The purpose of developing the serial interface industry standard jesd204a / jesd204b is to solve the problem of interconnecting the latest broadband data converter with other system ICs in an efficient and cost-effective way. The motivation is to standardize the interface by using adjustable high-speed serial interface and reduce the number of digital inputs / outputs between data converter and other devices, such as field programmable gate array FPGA and system level chip SOC.

The trend shows that the latest applications and the upgrading of existing applications are constantly in demand for broadband data converters with higher sampling frequency and data resolution. Transmitting and acquiring data to these broadband converters exposes a very big design problem, that is, the bandwidth limitation of existing I / O technology leads to more pins to be used in converter products. As a result, PCB design becomes more complex with the increase of interconnect density. The challenge is to control electrical noise while routing a large number of high-speed data signals, as well as the ability to provide GSPS level broadband data converter sampling frequency, use less interconnection, simplify PCB layout problems and achieve smaller size without reducing the overall system performance.

Market forces conTInue to press for more features, functionality, and performance in a given system, driving the need for higher data-handling capacity. The high speed analog-to-digital converter and digital-to-analog converter-to-FPGA interface had become a limiting factor in the ability of some system OEMs to meet their next generation data-intensive demands. The JESD204B serial interface specification was specifically created to help solve this problem by addressing this critical data link. Figure 1 shows typical high speed converter-to-FPGA interconnect configurations using JESD204A/JESD204B.

Market forces continue to put pressure on a given system to have more features and functions and better performance, driving the demand for higher data processing capacity. High speed analog-to-digital converter and digital to analog converter to FPGA interface have become the limiting factors for some system OEMs to meet the needs of next-generation massive data processing. Jesd204b serial interface specification is specially established to solve this key data link problem. Figure 1 shows a typical high-speed converter to FPGA interconnect configuration using jesd204a / jesd204b.

Some key end-system applications that are driving the deployment of this specification, as well as a contrast between serial low voltage differential signaling (LVDS) and JESD204B, are the subject of the remainder of the article.

The rest of this paper will discuss some key terminal system applications that promote the development of the specification, as well as the comparison between serial low voltage differential signal (LVDS) and jesd204b.

Figure 1. Typical high speed converter to FGPA interconnect configurations using JESD204A/JESD204B interfacing (Source: Xilinx®)。

Figure 1. Typical high speed converter to FGPA interconnect configuration using jesd204a / jesd204b interface (source: Xilinx ®)。

The Applications Driving the Need for JESD204B

Application drives demand for jesd204b

Wireless Infrastructure Transceivers

Wireless infrastructure transceiver

OFDM-based technologies, such as LTE, used in today’s wireless infrastructure transceivers use DSP blocks implemented on FPGAs or SoC devices driving antenna array elements to generate beams for each individual sub- scriber’s handset. Each array element can require movement of hundreds of megabytes of data per second between FPGAs and data converters in both transmit or receive modes.

At present, the wireless infrastructure transceiver adopts OFDM based technologies such as LTE, which uses DSP modules deployed with FPGA or SOC devices to generate beams for each user’s mobile phone by driving antenna array elements. In transmit and receive mode, each array element may need to transmit hundreds of megabytes of data between FPGA and data converter per second.

Software-Defined Radios

Software Defined Radio

Today’s software-defined radios utilize advanced modulation schemes that can be reconfigured on the fly, and rapidly increasing channel bandwidths, to deliver unprecedented wireless data rates. Efficient, low power, low pin count FPGA-to-data converter interfaces in the antenna path play a critical role in their performance. Software-defined radio architectures are integral to the transceiver infrastructure for multicarrier, multimode wireless networks supporting GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA.

Today’s software defined radio technology uses advanced modulation schemes, can be reconfigured immediately, greatly increases the channel bandwidth and provides the best wireless data rate. High efficiency, low power consumption and low pin count FPGA to data converter interface in antenna path plays a decisive role in performance. The software defined radio architecture has been integrated with the transceiver infrastructure for multi carrier and multi-mode wireless networks, supporting GSM, edge, W-CDMA, LTE, CDMA2000, WiMAX and TD-SCDMA.

Medical Imaging Systems

Medical imaging system

Medical imaging systems including ultrasound, computational tomography (CT) scanners, magnetic resonance imaging (MRI), and others generate many channels of data that flow through a data converter to FPGAs or DSPs. Continually increasing I/O counts are driving up the number of components by requiring the use of interposers to match FPGA and converter pin out and increasing PCB complexity. This adds additional cost and complexity to the customer’s system that can be solved by the more efficient JESD204B interface.

Medical imaging systems include ultrasound, computed tomography (CT) scanners, magnetic resonance imaging (MRI), etc. these applications generate many channels of data, which flow through the data converter to FPGA or DSP. The continuous growth of the number of I / O channels requires the use of interpolators to match the pin outputs of FPGA and converter, forcing the number of components to increase and complicating PCB. This increases the cost and complexity of the customer system; These problems can be solved by using a more effective jesd204b interface.

Radar and Secure Communications

Radar and secure communications

Increasingly sophisticated pulse structures on today’s advanced radar receivers are pushing signal bandwidths toward 1 GHz and higher. Latest generation active electronically scaled array (AESA) radar systems may have thousands of elements. High bandwidth SERDES-based serial inter- faces are needed to connect the array element data converters to the FPGAs or DSPs that process incoming and generate outgoing data streams.

At present, the pulse structure of advanced radar receiver is becoming more and more complex, forcing the signal bandwidth to rise to 1 GHz or higher. The latest active electronically adjusted array (AESA) radar system may contain thousands of components. The high bandwidth SerDes serial interface is used to connect the array element data converter with FPGA or DSP, process the received data stream, and send the processed data stream.

Serial LVDS vs. JESD204B

Comparison between serial LVDS and jesd204b

Choosing Between Series LVDS and JESD204B Interface

Select between serial LVDS and jesd204b interface

In order to best select between converter products that use either LVDS or the various versions of the JESD204 serial interface specification, a comparison of the features and capabilities of each interface is useful. A short tabular comparison is provided in Table 1. At the SERDES level, a notable difference between LVDS and JESD204 is the lane data rate, with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing the high level features like multidevice synchronization, deterministic latency, and harmonic clocking, JESD204B is the only interface that provides this functionality. Systems requiring wide bandwidth multichannel converters that are sensitive to deterministic latency across all lanes and channels won’t be able to effectively use LVDS or parallel CMOS.

In order to make the best choice between converter products using LVDS and multiple versions of jesd204 serial interface specification, it is very useful to compare the characteristics and functions of each interface. Table 1 compares the interface standards in a simple table form. At the SerDes level, the significant difference between LVDS and jesd204 is the channel data rate. Jesd204 supports more than three times the serial link rate per channel as LVDS. When comparing advanced functions such as multi device synchronization, delay determination and harmonic clock, jesd204b is the only interface to provide these functions. Systems where all paths and channels are sensitive to determining delay and require broadband multichannel converters will not be able to effectively use LVDS or parallel CMOS.

Table 1. Comparison Between Serial LVDS and JESD204 Specifications

Table 1. Comparison of serial LVDS and jesd204 specifications

LVDS Overview

LVDS overview

LVDS is the traditional method of interfacing data converters with FPGAs or DSPs. LVDS was introduced in 1994 with the goal of providing higher bandwidth and lower power dissipation than the existing RS-422 and RS-485 differential transmission standards. LVDS was standardized with the publication of TIA/EIA-644 in 1995. The use of LVDS increased in the late 1990s and the standard was revised with the publication of TIA/EIA-644-A in 2001.

LVDS is a traditional method to connect data converter with FPGA or DSP. LVDS was released in 1994. Its goal is to provide higher bandwidth and lower power consumption than the existing RS-422 and RS-485 differential transmission standards. With the release of TIA / eia-644 in 1995, LVDS became the standard. In the late 1990s, the utilization rate of LVDS increased, and with the release of TIA / eia-644-a in 2001, LVDS standard also issued a revised version.

LVDS uses differential signals with low voltage swings for high speed data transmission. The transmitter typically drives ±3.5 mA with a polarity matching the logic level to be sent through a 100 Ω resistor, generating a ±350 mV voltage swing at the receiver. The always-on current is routed in different directions to generate logic ones and zeros. The always-on nature of LVDS helps eliminate simultaneous switching noise spikes and potential electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. The differential nature of LVDS also provides considerable immunity to common-mode noise sources. The TIA/EIA-644-A standard recommends a maximum data rate of 655 Mbps, although it predicts a possible speed of over 1.9 Gbps for an ideal transmission medium.

LVDS uses low voltage swing differential signal for high-speed data transmission. The typical value of the current driven by the transmitter is ± 3.5 ma. The logic level with matched polarity is sent through a 100 Ω resistor, generating a ± 350 MV voltage swing at the receiver end. The current is always on and routed in different directions to produce logic 1 and logic 0. The always on characteristic of LVDS helps to suppress synchronous switching noise spikes and potential electromagnetic interference – which may be generated by the switching action of transistors in single ended technology. The characteristics of LVDS difference also provide effective suppression for common mode noise sources. Although the standard predicts that the rate may exceed 1.9 Gbps in an ideal transmission medium, the TIA / eia-644-a standard recommends a maximum data rate of 655 Mbps.

The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier, has created several issues with the LVDS interface (see Figure 2)。 The bandwidth of a differential LVDS wire is limited to about 1.0 Gbps in the real world. In many current applications, this creates the need for a substantial number of high bandwidth PCB interconnects, each of which is a potential failure point. The large number of traces also increases PCB complexity or overall form factor, which raises both design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth hungry applications.

The significant increase in data channel and speed between FPGA or DSP and data converter – especially those applications discussed earlier – exposes some problems in LVDS interface (see Figure 2). In reality, the bandwidth of differential LVDS line is limited to about 1.0 Gbps. In many current applications, this limitation leads to the need for many high bandwidth PCB interconnects, and each place may fail. A large number of routing also increases the complexity or overall size of PCB, resulting in an increase in design and manufacturing costs. In some applications with huge bandwidth demand, data converter interface has become a constraint to meet the required system performance.

Figure 2. Challenges in system design and interconnect using parallel CMOS or LVDS.

Figure 2. System design and interconnection challenges brought by using parallel CMOS or LVDS.

JESD204B OVERVIEW

Jesd204b overview

The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology with the goal of providing a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling single line pair communications at a much higher speed.

Jesd204 data converter serial interface standard was established by jc-16 Interface Technical Committee of JEDEC Solid State Technology Association. The goal is to provide higher speed serial interface, improve bandwidth and reduce the number of digital input and output channels between high-speed data converter and other devices. The standard is based on the 8B / 10B coding technology developed by IBM. It does not need frame clock and data clock and supports single line to line communication at a higher rate.

In 2006, JEDEC published the JESD204 specification for a single 3.125 Gbps data lane. The JESD204 interface is self-synchronous, so there is no need to calibrate the length of the PCB wire traces to avoid clock skew. JESD204 leverages the SERDES ports offered on many FPGAs to free up general- purpose I/O.

In 2006, JEDEC released the jesd204 specification to achieve a rate of 3.125 Gbps on a single data channel. The jesd204 interface is self synchronous, so there is no need to calibrate the PCB wiring length to avoid clock skew. Jesd204 relies on SerDes ports provided by many FPGAs to release general-purpose I / O.

JESD204A, published in 2008, adds support for multiple time-aligned data lanes and lane synchronization. This enhancement makes it possible to use higher bandwidth data converters and multiple synchronized data converter channels and is particularly important for wireless infrastructure transceivers used in cellular base stations. JESD204A also provides multidevice synchronization support that is useful for devices, such as medical imaging systems, that use large numbers of ADCs.

Jesd204a was released in 2008, adding support for multi-channel timing consistent data channels and channel synchronization. This enhancement makes it possible to use higher bandwidth data converter and multi-channel synchronous data converter channels, and is particularly important for wireless infrastructure transceivers for cellular base stations. Jesd204a also provides multi device synchronization support, which is conducive to applications using a large number of ADCs such as medical imaging systems.

JESD204B, the third revision of the spec, increases the maximum lane rate to 12.5 Gbps. JESD204B also adds deterministic latency, which communicates synchronization status between the receiver and transmitter. Harmonic clocking, also introduced in JESD204B, makes it possible to derive a high speed data converter clock from a lower speed input clock with deterministic phasing.

Jesd204b is the third revision of the specification, which increases the maximum channel rate to 12.5 Gbps. Jesd204b also adds support for determining delay, which enables synchronous communication between receiver and transmitter. Jesd204b also supports harmonic clock, which makes it possible to obtain high-speed data converter clock through low-speed input clock according to the determined phase.

Conclusion

conclusion

The JESD204B industry serial interface standard reduces the number of digital inputs and outputs between high speed data converters and FPGAs and other devices. Fewer interconnects simplify layout and make it possible to achieve a smaller form factor (see Figure 3)。 These advantages are important for a wide range of high speed data converter applications, such as wireless infrastructure transceivers, software-defined radios, medical imaging systems, and radar and secure communications. Analog Devices is an original participating member of the JESD204 standards committee and we have concurrently developed compliant data converter technology and tools along with a comprehensive product roadmap offering. By providing customers with products that combine our cutting edge data converter technology along with the JESD204A/JESD204B interface, we expect to enable customers to solve their system design problems, while taking advantage of this significant interfacing breakthrough.

Jesd204b industrial serial interface standard reduces the number of digital input and output channels between high-speed data converter and FPGA and other devices. Fewer interconnects can simplify layout and routing and make it possible to achieve smaller size design (see Figure 3). These advantages are important for many high-speed data converter applications, such as wireless infrastructure transceivers, software defined radios, medical imaging systems, radar and secure communications. ADI is a founding member of jesd204 Standard Committee. We have also developed compatible data converter technologies and tools, and launched a comprehensive product roadmap. By providing customers with products that combine our advanced data converter technology and integrated jesd204a / jesd204b interface, we are expected to make full use of this major interface technology breakthrough to help customers solve system design problems.

Figure 3. JESD204 with its high speed serial I/O capability solves the system PCB complexity challenge.

Figure 3. Jesd204 has high-speed serial I / O capability and can solve the complexity challenge of system PCB.

About the Author

Introduction to the author

George Diniz is a product line manager in the High Speed Digital- to-Analog Converters Group at Analog Devices in Greensboro, NC. He leads a team responsible for the development of JESD204B receiver and transceiver interface cores, which are integrated into high speed analog-to-digital and digital-to-analog converter products. He has 25 years of experience in the semiconductor industry and has held various roles in design engineering and product line management. Before joining ADI, George was a design engineer at IBM, where he was engaged in mixed-signal design of custom SRAM macros, PLL, and DLL functions for power PC processors. He has an M.S.E.E. from North Carolina State University and a B.S.E.E. from Manhattan College. For recreation, George enjoys outdoor activities, restoring automobiles, and running. He can be reached at [email protected]

George Diniz is the product line manager of ADI’s high-speed digital to analog converter division (Greensboro, North Carolina). His development team is responsible for developing the jesd204b receiver and transceiver interface core for integration into high-speed analog-to-digital and digital to analog converter products. He has 25 years of working experience in the semiconductor industry and has held various positions such as design engineering and product line management. Before joining ADI, George was a design engineer at IBM. He was engaged in mixed signal design of custom SRAM macros, PLL and DLL functions for power PC processors. He holds a master’s degree in Electrical Engineering (MSEE) from North Carolina State University and a bachelor’s degree in Electrical Engineering (BSEE) from Manhattan College. In terms of entertainment, George likes outdoor activities, repairing cars and running.

Leave a Reply

Your email address will not be published. Required fields are marked *