Certus ™- Nx brings the advantages of lattice nexus FPGA technology platform to new markets, mainly for applications requiring PCI Express and Gigabit Ethernet interconnection. The new product line has two models, with 17k and 39K logical units respectively. Larger certus ™- Nx-40 also provides PCIe Gen2 interface, which can connect host processor, wireless or wired communication chip and many other devices. Both models support Gigabit Ethernet through hard core, which improves performance and efficiency. While the package size of the new product is much smaller than that of the competitive product, the I / O density has doubled.

The nexus platform is unique in the fd-soi process. This is very different from the previous CMOS process and can greatly reduce power consumption. As shown in Figure 1, certus ™- Nx consumes 3-4 times less power than similar products of Intel and Xilinx. Certus ™- Nx configuration time is very short, which can make the system start quickly. The device also has verification and encryption hardware modules to improve security.

Intel certus ™- Nx products can be connected to analog motors and sensors

Figure 1 Lattice Certus ™- Nx device. Compared with similar FPGA products of Intel and Xilinx, certus ™- The power consumption of NX is reduced by 70-75%. This power consumption is measured for PCIe Gen2 interface with TJ = 85 º C and 125MHz under strict test environment.

Certus ™- Nx is mainly oriented to various control and computing applications in the network, including automatic industrial equipment running at the edge of the network, 5g communication infrastructure and cloud data center. The FPGA can handle a variety of communication protocols, and its security characteristics are very suitable for networked devices. In many cases, the device can share the load of neural network (AI) when performing communication tasks. Certus ™- The NX can also be connected to analog motors and sensors.

Product overview

Certus ™- Nx FPGA provides flexible I / O and enough gates to implement various protocols. The device has up to 39K logic units to provide sufficient logic for various designs, so as to use embedded DSP core to realize neural network or other acceleration functions. The hardware encryption module can speed up the elliptic curve (ECDSA) encryption and AES batch encryption algorithms for code authentication. The chip also includes hard logic for clock and data recovery (CDR), supports Ethernet data transmission rate up to 1 Gbps, and better supports Ethernet design. By combining the module with a sufficient number of LUTS to realize Ethernet protocol, the chip can also realize sgmii connection with external PHY chip.

As shown in Figure 2, certus ™- The nx-40 includes the hard logic of the PCIe Gen2 controller for high-speed communication. The interface can connect a single channel up to 5 Gbps. Both models have two 12 bit successive approximation (SAR) analog-to-digital converters (ADCs) with a rate of up to one million samples per second (MSPs). For other protocols, the programmable I / O of the chip can realize a single interface and differential interface up to 1.5gbps, including LVDS, subLVDS and DRAM (up to ddr3-1066). For these interfaces, the controller must be implemented using LUT resources. The logic structure of the chip includes LUT, embedded memory and 18×18 bit multiplier for DSP function. There is a large ram outside the chip logic mechanism, which can provide up to 2.5 Mbit of additional storage space.

Intel certus ™- Nx products can be connected to analog motors and sensors

Figure 2 Certus ™- Nx schematic diagram. The new FPGA has a hard core module for AES and elliptic curve encryption, clock and data recovery (CDR) for Gigabit Ethernet (sgmii), PCIe Gen2 controller and analog-to-digital converter (ADC).

Fd-soi process can realize back bias, and the leakage is reduced by 75% compared with CMOS process. Operating at 1.0V will reduce the effective power. The process also improves the reliability of the chip. Since FPGA stores its configuration in SRAM, random soft errors may cause device failure (SEU). Compared with CMOS, fd-soi process can eliminate more than 99% soft errors of SRAM and fundamentally avoid the occurrence of SEU.

Certus ™- Nx products are available in a variety of packages, of which the minimum size is only 6×6 mm. The low power feature of the design reduces the number of power connections and grounding, leaving more space for I / O. The smallest package size has 82 I / OS, and the largest package (14×14 mm) has 192 I / OS. Lattice also reduces the time required to load FPGA configurations into SRAM, thereby reducing startup time. If Quad SPI is used to connect external flash memory, certus ™- The startup time of nx-40 is less than 14ms. I / O can complete initialization in 3 milliseconds.

Product comparison

For applications that require PCIe, certus ™- Nx-40 competes with two other products in the market, namely Intel’s cyclone V and Xilinx artix-7 series FPGA. The latter two are FPGA with hard core PCIe interface and 28nm CMOS process. For this product, we all chose models with 50000 logical units for comparison, because their lower level smaller models only have 33000 logical units, which is far lower than that of certus ™- NX。 As shown in Table 1, the total storage capacity of the two competing products is slightly larger, the number of corresponding gates is also larger, and more DSP modules are provided.

FPGA for PCIe design. Certus ™- Nx provides better encryption performance, supports Ethernet and faster I / O speed* This range corresponds to different package sizes* This data is measured for PCIe Gen2 interface under strict test environment with TJ = 85 º C and 125MHz.

Certus ™- Nx performs well in many ways. It supports optimal encryption, provides user mode AES acceleration, and FPGA configuration bit stream verification (ECDSA) and encryption. The two products of Intel and Xilinx lack verification and only support AES configuration. Although the two PCIe GEN1 channels of the cyclone FPGA can provide the same total bandwidth, it does not provide PCIe Gen2 support, and it does not provide a hard core CDR module for Ethernet design. Certus ™- Nx has the highest I / O speed, and its package size is only one third of that of other products, which can greatly save the circuit board area.

For applications that do not require PCIe interface, certus FPGA competes with cyclone V E series and spartan-7 series. Table 2 compares certus ™- Nx-17 is similar to the number of logical units in the above series. Although certus ™- Nx has fewer logical units, but its storage space is larger. It has both embedded memory and external large memory, so that it can buffer more data or store larger neural networks. As before, certus ™- Nx is more prominent in encryption and I / O speed. Its small package size of 6×6 mm requires less than a quarter of the circuit board area of the two competing products, and the I / O density is about twice that of them. Certus ™- Nx is also the only FPGA with Ethernet hard core in this group of products.

FPGA is used for network edge devices. Certus ™- Nx has smaller package size, more than 100 times higher anti soft error performance than competitive products, and more than 10 times shorter configuration time.

Certus ™- Nx series products take advantage of its unique fd-soi technology and have great advantages in power consumption and anti soft error rate. In the basic design and implementation, certus ™- The power consumption of NX chip is 3-4 times lower than that of Intel and Xilinx products. Lattice’s chip has only 19 soft error failures (FIT), and its stability is 160 times that of the other two products. When starting from Quad SPI memory, certus ™- Nx configuration speed is also 10 times faster than competitive products. The other two products do not provide the instantaneous start function of I / O pin, but in certus ™- The response time on NX is only 3 ms. Lattice also offers a collection of sensai solutions that enable customers to develop neural networks using Caffe or tensorflow tools. We look forward to lattice’s future at certus ™- These functions are available on NX series devices. Sensai also includes RTL overlay, which can use integer or binary calculation to program FPGA and carry out neural network reasoning.

conclusion

Certus ™- Nx’s many advantages can directly improve end products. Its small size package of 6×6 mm can be used for smaller circuit board design or save space to add new system functions. The package size of similar competitive FPGA products is 10×10 mm to 13×13 mm, and the same is true for models with relatively few gates. Although certus ™- Nx is small in size, but can provide higher I / O density, providing great flexibility for circuit board designers. The chip adopts unique fd-soi technology, which has lower power consumption than CMOS process, and realizes comprehensive optimization of power consumption and size.

For communications and other applications, certus ™- Nx provides hard logic implementation of PCIe Gen2 and Gigabit Ethernet interfaces, simplifying the implementation of these common standards. The flexible I / O pin rate of the device is up to 1.5 Gbps, which can process communication faster than competitive FPGA. In order to improve the security of networked devices, this series of FPGA also has encryption module to accelerate batch encryption AES and elliptic curve (ECDSA) verification. The module can also verify the external configuration memory to realize safe startup. Except certus ™- Except NX, no FPGA with less than 100k logic units has ECDSA module. Certus ™- Nx initialization speed is also 10 times faster than competitive devices, greatly reducing the time for end users to wait for their devices to start.

The new FPGA has an A / D converter, which can be combined with analog sensors in IOT design. Combined with the programmable output in PWM mode, the ADC is very suitable for motor control. In addition, certus ™- Nx can be used as an accelerator to implement neural networks through specific algorithms on the lattice sensai platform or logic units. In these designs, FPGA can be directly connected to host processor through high-speed PCIe interface

Only a small number of pins are used. Fd-soi process has natural immunity to soft errors, so certus ™- Nx is ideal for aerospace applications. However, lattice has a small number of device multipliers, which is not suitable for DSP intensive applications.

Certus ™- Nx is the second product based on lattice nexus platform, which brings the advantages of fd-soi process to a wide range of application fields. These general-purpose FPGAs provide low-power features, small package size and flexible I / O, as well as PCIe Gen2, Gigabit Ethernet interface and advanced encryption functions. They are very suitable for all kinds of network edge applications, including smart home, Internet of things and consumer electronics networks. In addition, they can also be used in motor control and other simulation applications, or provide low-power and high-performance acceleration services for AI and other special algorithms. Lattice’s continuous focus on this field continues to provide unique and innovative functions for certus ™- Nx stands out in the fierce competition.

Editor in charge: PJ

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