In late August, sarinx released the world’s largest FPGA device: virtex ultrascale + vu19p.
The FPGA is based on TSMC’s 16 nanometer process, which integrates 35 billion transistors, and has the highest single device logic density and I / O quantity at that time: more than 2000 user programmable pins, 9 million programmable logic units, 224mb on-chip memory and 3800 DSP units. The vu19p is 60% larger than its predecessor, the virtex ultrascale 440 FPGA based on the 20 nm process.
However, Xilinx’s vu19p only occupied the throne of “the world’s largest FPGA” in less than three months. In early November, Intel announced the introduction of stratix10 GX 10m FPGA, which has become the largest FPGA chip in the world.
Compared with 3.5 billion transistors, 9 million programmable logic units (LE) and 2072 programmable I / O pins of Xilinx vu19p, Intel stratix10 GX 10m is based on its own 14 nm process, with 43.3 billion transistors, 10.2 million programmable logic units and 2304 programmable I / O, which are superior to vu19p in these aspects.
Before that, Intel’s largest FPGA device was the Stratix 10 GX 2800, which has 2.75 million programmable logic units and 1160 programmable I / O. In addition, Intel’s FPGA agilex also has about two million programmable logic units. Compared with these two devices, the capacity of stratix10 GX 10m has soared nearly four times.
As for the “world’s largest FPGA”, on the one hand, it is because the super large FPGA plays an indispensable role in the field of hardware simulation and prototype verification, which has been analyzed in detail in the previous article; on the other hand, it is more like the chip manufacturers are “showing muscle”, because the manufacturing of this super large chip requires complex system integration and packaging technology.
For SIRINGS, they always use the so-called stack silicon interconnection technology (SSI). The main disadvantage of this technology is that there is a hard boundary between multiple silicon wafers. They can only be interconnected and communicated through the silicon intermediate layer, which leads to obvious performance bottlenecks. This is described in detail in “3D FPGA Technology: Black technology continuing Moore’s law”. In the latest ACAP device of Xilinx, this problem is optimized.
In contrast, Intel uses 3D system level packaging technology, the core of which is EMI, also known as embedded multi-core interconnection bridge. Instead of introducing an additional silicon intermediary layer, EMI only adds a silicon bridge at the edge connection of two silicon wafers, and customizes the I / O pins at the edge of the silicon wafers to match the bridging standard. Compared with SSI, emib has two obvious advantages: the complexity of system manufacturing is greatly reduced, and the transmission delay between silicon chips is greatly reduced.
EMI B has been used in Stratix 10 FPGA for a long time. For example, in MX series, the so-called “3D stack type high bandwidth memory”, or HBM, is integrated through EMI B. In addition, emib can be used to connect various transceiver units (Intel calls them different tiles). This kind of heterogeneous integration method based on emib is very flexible. It uses the way of chip set, so that the same FPGA silicon chip can be matched with different transceiver, HBM, CPU and other units for rapid system level chip integration.
In this release of stratix10 GX 10m, Intel for the first time connected two large FPGA silicon chips with 5.1 million programmable logic units through emib, thus forming a large FPGA. The two FPGA chips are interconnected through 25920 emib data interfaces. Each data connection can provide 2gbps throughput, so the overall communication throughput of the system is as high as 6.5tbps. This is actually announcing that emib technology can fully handle the throughput requirements of ultra-high bandwidth.
The 3D system level packaging technology adopted by Intel FPGA has higher requirements on chip yield, because although it is a heterogeneous integration technology, it depends on the isomorphism of each component. In other words, the FPGA programmable logic array itself is a whole silicon chip. However, we can see from the stratix10 GX 10m released this time that emib can also be used as the interconnection technology of isomorphic chips, thus greatly expanding the applicability of this 3D packaging technology. In addition, a single FPGA silicon chip can achieve 5.1 million logic units, which also shows that Intel 14 nanometer technology has been very mature.
It is worth noting that emib is not Intel’s only 3D Interconnect and integration technology. At the beginning of this year, Intel announced a real * 3D packaging technology called foveros, which can stack the bare chips of functional units such as CPU, GPU, DRAM and cache together and then package them into a complete chip. Foveros will be used on Intel’s Lakefield based on 10 nanometer process.
Although many people compare FPGA to building blocks, which can be used to implement various applications, making FPGA itself is not as simple as building blocks. From this “world’s largest FPGA”, we can see that there are too many cutting-edge technologies in it. Laoshi believes that in the near future, there will inevitably be larger and more complex FPGA devices, and the technology driving it will continue to promote the continuation of technology and civilization.