1 Introduction

Direct sequence spread spectrum technology has been widely studied and applied in the fields of communication, navigation, measurement and control. The spread spectrum modulation system requires the exact same pseudo-random code to be used for spreading and despreading at both ends of the transmitter and receiver. Therefore, the precise synchronization between the receiver’s local reference pseudo-code sequence and the received code sequence is the key to de-spreading the desired signal. The tracking performance of the code phase directly affects the accuracy of the spread spectrum ranging. The code phase tracking usually adopts the delay-locked loop method, that is, the local generator is used to generate phase leading and lagging code signals, which are correlated with the input spread spectrum signal, and the correlation results are compared to obtain the code phase error signal to control the code NCO generation and input. A local signal with the same code phase. Commonly used delay locking includes coherent DLL and non-coherent DLL. With the rapid development of large-scale integrated circuits, the application of non-coherent DLLs in all-digital pseudo-code tracking loops is increasingly widespread. In the literature, the incoherent tracking loop has been deeply studied, and a pseudo-code tracking loop that is more suitable for digital implementation is proposed compared with the conventional method. Its structure is shown in Figure 1.

Figure 1 Code tracking loop structure for GPS signal reception

In the tracking loop structure shown in Figure 1, in order to make the code tracking loop have a large tracking range and high tracking accuracy at the same time, multiple DLLs with different correlation spacings can be used. The initial tracking adopts a wide correlation spacing. After stable tracking, in order to improve the accuracy Use narrow correlation spacing. The above-mentioned methods for improving the performance of the code tracking loop all require generating a plurality of pseudo-code sequences with different delay relationships.

2. Conventional method

The leading and lagging pseudo-code generators used in the code tracking loop mostly use shift registers to generate pseudo-code sequences with different delays. The minimum delay interval of different pseudo-code sequences is determined by the maximum operating clock of the shift register. A basic criterion of a direct spread signal receiver is that the sampling rate cannot be an integer multiple of the pseudocode rate, and the delay between different pseudocode sequences is basically determined by the sampling rate. In order to obtain a narrower delay interval, the sampling frequency has to be multiplied as the working clock of the shift register.

Using a shift register to generate a pseudo-code sequence, the modification and adjustment of the delay interval are very inflexible. When the pseudo code rate is high (>80Mcps), the shift clock of the shift register must be limited by the maximum one-1: operation capability of the column FPGA device (the maximum clock frequency of Virtex5 is 550MHz), which cannot meet the 0.1chip delay. narrowly related requirements.

3. New delay control method

3.1 Algorithm principle

When implementing a digital phase-locked loop. A numerically controlled oscillator (NCO) is commonly used to replace the analog device VCO, which is easy to implement in an FPGA. The NCO is designed using the DDS principle, and its working process is as follows: the phase accumulator uses the frequency control word as the step to perform addition operations in the N-bit accumulator under the action of the NCO clock, and the low L bit of the code accumulator corresponds to a code slice, take the high bit of the resulting phase code to address the look-up table, and output the data stored in the look-up table. Referring to the idea of ​​numerical control NCO, this paper proposes a new method of generating pseudo-code sequences of full digital, which can complete the delay control of arbitrary precision only by changing the initial phase setting in the phase accumulator. It reduces the requirements for the operating clock frequency, and is easy to implement in digital devices such as FPGA and CPLD, which provides a strong guarantee for the improvement of the pseudo-code tracking algorithm.

Following the principle of the NCO algorithm, the logic block diagram of the pseudo-code sequence generation method is shown in Figure 2, which is mainly composed of a frequency word register, a phase accumulator and a pseudo-code storage table.

Figure 2 Logic block diagram of the new pseudo-code sequence generation method

Suppose the updated code frequency of the code tracking loop filter input is fc, then the output code frequency word: fw=Kf x fc Among them, the conversion coefficient Kf=2L/f3, f3 is the reference clock of the phase accumulator. When the required initial phase θ0 is set, the cyclic accumulation is performed with θ0 as the initial value at the rising edge of f3:

Among them, θk is the pseudo code phase output by the phase accumulator after the K-th accumulation.

Assuming that the length of the pseudo-code sequence is 1023, a complete pseudo-code cycle needs to be queried, and the table lookup address must take at least 10 bits (210=1024), so the upper 10 bits of the accumulator are taken as the address of the code table. Controls the pseudocode storage table to output pseudocode sequences. When the phase accumulator finishes accumulating one cycle, in order to ensure that the phases of the pseudo-code sequences of the two cycles before and after are continuous, the modulo operation can be performed according to the formula (3).

So far, the whole process of generating the pseudocode sequence is completed. The following focuses on the pseudo-code sequences obtained by different initial phases in the phase accumulator to obtain different delays

3.2 Generation of Different Delay Sequences

According to the above analysis, it can be known that 2L of the accumulator corresponds to a pseudo-code chip. Therefore, the required pseudo-code delay sequence can be obtained by setting different initial values ​​for the phase accumulator. For example, in order to improve the tracking range of the code tracking loop, the delay interval of 1/2 chip is selected in the initial tracking; after locking, in order to improve the tracking accuracy, the delay interval of 1/4 chip is adopted. The pseudo code generator (take N=42) is shown in Figure 3.

Figure 3 Flowchart of a method for generating pseudocode sequences with different delays

In Fig. 3, the output control of the pseudo-code sequence is realized through a 42-bit accumulator modulo 1023×232, and 232 corresponds to one pseudo-code chip. 1023 pseudo-code chips are stored in order to make up the code table. Use the upper 10 bits of the 42-bit accumulator as the address of the code table, look up the table and output the corresponding pseudo-code sequence. Pseudo-code sequences with different delays are distinguished by setting different initial values ​​for multiple pseudo-code accumulators. The initial value of 0 is the pseudo code sequence with a lag of 1/2 chip, that is, the pseudo code sequence with the largest delay chip; the initial value of 230 is the pseudo code sequence with a delay of 1/4 chip; the initial value is set to 231 is the real-time pseudo-code sequence; the initial value of 231+230 is the pseudo-code sequence of 1/4 chip ahead; the initial value of 232 is the pseudo-code sequence of 1/2 chip ahead. The regenerated pseudo-code cycle clock is generated by judging the chips of the pseudo-code sequence, and judges the result of the instant pseudo-code branch modulo 1023×232. When the pseudo-code address corresponds to the start bit, it outputs a high level, and at other times, it outputs a low level, so Generates a re-quasi-pseudocode periodic clock. With this method, pseudo-code sequences of various delays can be easily realized. And the delay accuracy is up to 1/232 chip. It can flexibly generate lead and lag pseudo-code sequences with different chip delays.

4. Design implementation and simulation verification

4.1 FPGA design and implementation

According to the structure of the logic block diagram shown in Figure 4, using the ISE design software of Xilinx Company, adopting the top-down modular design method, using VHDL to program and design each part of the pseudo-code sequence generation method, and then using ModelSim to design this method. The module does a comprehensive simulation. The final result is shown in Figure 4.

Figure 4 Simulation waveform diagram based on VHDL

Among them, 1_1_2_phase, 1_1_4_phase, pm_phase, e_1_4_phase, e_l_2_phaae represent the pseudocode phases corresponding to the lag, immediate and leading pseudocodes, respectively; l_l_2_code, l_1_4_code, pm_code, e_l_4_code, e_l_2_code respectively represent the generated lag, instant and leading pseudocode sequences.

Taking the implementation in xc4vsx35-12ff668 as an example, it is found by simulation that this module consumes 242 slice resources, accounting for 2% of the total slice resources of the entire FPGA, and consumes 4 input LuTs resources 393, accounting for only 1%, the consumption is small, and the complexity Low, easy to implement in digital devices such as FPGA and CPLD.

4.2 MATLAB simulation verification

Set the simulation parameters as follows: the sampling rate is 55MHz, and the code rate is 10.23Mcps. In the case of different carrier-to-noise ratios, the conventional shift register method and the method in this paper are used to simulate the second-order code tracking loop in Matlab. Without considering the Doppler frequency, the root mean square error of the code tracking loop is calculated, and the results are shown in Figure 5. The results show that the method proposed in this paper can guarantee the performance of the F-code tracking loop.

Fig. 5 Comparison of code tracking loop tracking errors between the method in this paper and the conventional method

5. Conclusion

The method proposed in this paper has been applied to a space measurement and control system. The method uses a similar NCO method to control the output pseudo-code sequence, and generates pseudo-code sequences with different delays through the setting of the initial phase, which is convenient for narrow correlation adjustment. Multiple pseudo-code delay sequences can be obtained by duplicating a single accumulating module and a code table, which facilitates the completion of algorithms for different code tracking loops. It has been proved by practice that it can achieve the narrow correlation extension requirements of arbitrary precision and has a wide range of applications.

The innovation of this paper: A new FPGA-based pseudo-code sequence generation method is proposed, which can generate pseudo-code sequences with different delays. It breaks through the limitation of sampling rate and can meet the requirements of different code tracking loop algorithms. Through the design and implementation, it shows that the method consumes less resources, and the simulation verifies that the pseudo-code tracking loop using this method has good tracking performance.

Responsible editor: gt

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