In the process of signal processing, we usually convert analog signal into digital signal for processing or transmission. The original data is collected by sampling method, and the analog signal is converted into digital signal through a / D conversion. However, due to the large number of code bits, such digital signals occupy more bandwidth in the transmission process, and the transmission rate is also low. In order to improve the transmission efficiency, it is necessary to quantify the original data. In practice, non-uniform quantization is usually used. There are two kinds of correspondence between input amplitude and quantized output data. One is the law used in North America and the other is the A law used in Chinese mainland. A-Law compression is important in speech compression coding of digital telephone communication. How to realize fast compression has become the key of practical application. With the development of VLSI (very large scale integrated circuit), especially FPGA technology, the implementation of various compression codes based on FPGA shows its unique advantages and wide application prospects. In this paper, according to the characteristics of the algorithm from 13 broken lines, an improved parallel data processing algorithm is proposed, which is suitable for the implementation of coding pipelining. It is implemented in FPGA with VHDL language. It is verified and simulated by Quartus II 6.0 platform. The simulation results are analyzed and the performance of the system is evaluated. The superiority and efficiency of the algorithm are verified.
Fig. 1 13 broken line diagram
3. Design idea of coding pipeline algorithm
This design improves the conventional algorithm from the point of view of pipeline operation. The former stage completes the corresponding bit calculation and transmits the result to the next level. After that, it enters into the coding operation of the next group of data, so as to achieve the purpose of flow shop. Because each module has independent function, it is suitable for modular design.
3.1 polarity code C1
Indicates that the sample value of input signal is in 8
4. Specific implementation
Figure 2 system block diagram
In Fig. 2, an improved parallel data processing algorithm suitable for encoding pipeline operation is implemented in the system block diagram of Fig. 2, which is implemented by FPGA. The system is mainly composed of state machine and compare unit Under the control of state machine, the seven modules of comp7 perform pipeline data processing in parallel. In other words, under the control of state machine, in a CLK clock pulse, seven units are processing data at the same time. After processing, the output of the former comp unit is used as the input of the latter comp unit, and the next set of data processing is carried out immediately after the arrival of the next CLK clock pulse. According to this way, it can be processed in turn to achieve the purpose of pipeline operation. The following is the implementation of the system.
4.1 state machine
In order to make the comp modules work orderly and ensure the correct and stable data transmission, the state machine is introduced to control the data reading and writing of each module.
Fig. 4 flow chart of comp unit (paragraph code unit)
5. Verification results
On QuartusII 6.0 development platform, the function and timing of the design are verified by using cyclone family chips. The timing results are as follows (Fig. 5)
Figure 5 timing simulation results
It can be seen from Figure 5 that under the CLK = 100MHz clock, after the first data + 1248 (110011100000) input, after 14 clock cycles, the corresponding 8-bit code with polarity is 11110011. After the 14th clock cycle, a group of data compression coding is completed every two clock cycles. In this way, the pipeline operation of coding is realized and the efficiency of data processing is improved. Through the verification of the data, the correctness of the data operation is proved, and the expected design effect is achieved.
Evaluate the operation rate of the system and determine the bottleneck channel, as shown in Figure 6
Figure 6 time sequence analysis diagram
As can be seen from the timing simulation diagram in Fig. 5, a group of coding is completed every two clocks. This is because each module needs to read and write two clocks to complete data processing. As can be seen from Figure 6, the maximum time consumption of signal processing occurs in the comp7 module, which takes 12.900 ns, which means that the maximum time consumption of the whole module is 12.900 ns. The maximum clock frequency Fmax is 155.04mhz and the fastest encoding rate is 77.52mbyte/s.
In practical speech communication, due to the relatively low speech sampling rate, the general coding rate is 64kbit / S. in A-Law compression coding, the parallel data processing algorithm proposed in this paper is used to realize the pipeline operation of coding with VHDL, and the fastest coding rate is 77.52mbyte/s. Therefore, the use of this algorithm in multi-channel signal acquisition can greatly improve the efficiency of the system.
The innovation of this paper: This design improves the conventional algorithm from the perspective of pipeline operation, and realizes the design and verification of pipeline operation algorithm on FPGA.
Editor in charge: GT