PCIe link protocol uses “end-to-end data transmission mode”, and TX (transmission logic) and Rx (reception logic) are contained in both the transmitter and receiver.PCIe protocol adopts a hierarchical structure, which is divided into transaction layer, data link layer and physical layer. Two interconnected devices in PCIe communicate in the form of transaction, which means to realize some information transmission between devices.
The customized sending sequence composed of one or several packets is realized through transaction packet (TLP). The functions of each layer of the protocol are as follows:
1. Physical layer: electrical characteristics. It uses two unidirectional low-voltage differential pairs of signals to realize data transmission, and also undertakes 8B / 10B data encoding and decoding,That is, 8 bits of valid data are contained in 10 bits on the PCIe link
2. Data link layer: assemble and disassemble the TLP transmitted by this layer as an intermediate layer to serve the upper and lower layers.
3. Transaction layer: accept the request sent from the software side, generate the request packet and transmit it to the data link layer. At the same time, it receives data packets from the data link layer,
Transfer to the software, that is, sub assemble and assemble the TLP.
PCIe protocol communication block diagram is as follows:
The user logic is directly connected with the PCI Express transaction layer interface, and can send or receive transaction layer data packets to realize the bar (base address register) space access function and DMA read-write function. When the computer reads and writes the memory in the bar space of the board, it is the CPU (computer) that sends the command of memory mapping address to write the register. The command includes memory mapping address byte enable and register content. After the corresponding TLP endpoint of PCIe receives the TLP and writes the register content to the corresponding local register, the transaction ends.
When the CPU sends the command to read the memory mapping address register, the command includes the memory mapping address byte enable to generate the corresponding TLP. After receiving the TLP, the endpoint will generate a response TLP (including data) to complete the packet transmission, extract its payload and assign it to the specified register, and the transaction ends. The user logic design structure is shown in Figure 2:
The PCIe integrated endpoint module core in the figure above can be directly implemented by using the PCIe IP core in the FPGA. What we need to implement in the FPGA is mainly some modules connected with the PCIe IP core in the figure above.