Nowadays, the main factor causing cost changes in digital display equipment is the display screen. In the design stage, continuously promoting the decision-making of platform based display design can greatly reduce the procurement cost. OEM can get a big discount from one supplier if they can support multiple display sizes. In order to support the specifications of a variety of display vendors, OEMs can create a competitive situation to get lower prices. The cost savings of these two schemes are greater than the price increase caused by the need for additional devices, such as FPGA based on platform design. In addition, the support of multiple suppliers reduces the risk of continuous supply.
Some considerations of platform based display design
Figure 1: reconfigurable FPGA supports multiple screen sizes, I / O standards, and changing image processing algorithms.
Advanced FPGA can meet all these requirements and provide flexible solutions. The most effective FPGA solutions are those for image processing, memory control and I / O support in display design, which can provide comprehensive and reprogrammable platform based solutions.
FPGA with embedded DSP solution
The key of system design lies in the balance of CPU / software, ASIC, ASSP and FPGA solutions, which function is the best for the programmable solution in the platform based display design. Generally, when selecting programmable devices, it is necessary to evaluate the requirements of the following three kinds of circuits:
1. Low swing differential signaling (RSDs) and low voltage differential signaling (LVDS) support screen interface;
2. Ddrsdram supports image processing memory;
3. The function and performance of DSP for image processing.
The FPGA solutions that meet these requirements are listed in Figure 1. Input to FPGA is image processing chip and other ASSP, such as wireless Ethernet. The output includes the screen driving circuit and display timing generator. In addition, the FPGA block in the middle of the figure realizes the image processing function and supports the screen, size and regional requirements of various manufacturers.
In the input part, FPGA helps designers bridge the ASSP function to the graphics processor or system processor. Examples of bridging include wireless Ethernet (802.11a/g, HIPERLAN2) and user interface control logic. The next generation of display devices and projectors may support wireless Ethernet via 802.11a or HIPERLAN2. In addition, customized user interface logic can differentiate the display products of developers from those of competitors. Both functions are bridged or controlled by an FPGA solution.
For the image processing part, FPGA provides scaling, screen aspect ratio conversion, color space conversion, noise reduction and other video frame DSP functions to support a variety of different sizes of displays and manufacturers. These image processing algorithms can be proprietary, such as the sharpness enhancement of the contour, so that the product differentiation can be formed due to the continuous improvement of the algorithm.
FPGA with embedded DSP can easily reprogram image processing. Some less than $10 FPGAs with embedded DSP support 3000 Mac, less than 0.3 cents per MMAC, which can save costs for image processing functions. FPGA with embedded DSP function contains several multiplication modules, and some FPGA also have embedded adder, subtractor and accumulator, which greatly enhance the image processing function. Although low-cost FPGA works at less than 300 MHz system clock frequency, high DSP throughput (3000 MAC) can be achieved by parallel execution of multiple DSP functions by multiple DSP modules on the chip.
In addition, FPGA can provide memory control and interface for ddrsram image processing frame buffer. Compared with traditional SDR (single data rate), DDR memory has double throughput at the same clock rate. Ddrsdram is usually used in frame buffer memory, which needs a large number of low-cost and fast memory for image processing.
Table 1: electrical characteristics of RSDS and LVDS.
The DM data shielding function of ddrsdram device is used to simplify the data processing of graphic display application. Instead of performing read, modify, and write cycles to change a part of a wide word, masked write cycles and DM masked signals are used together to enable and disable the writing of individual bytes in a wide word. Because a single write cycle replaces the read, modify and write cycles, the improvement of system performance is obvious. Write masking simplifies changing the selected bits in a data block and increases the performance of display color management tasks.
It is very easy to implement DDR memory interface with general I / O and logic FPGA at low clock speed and less than 100MHz. However, in high frequency, FPGA is required to have a proprietary circuit, which can reliably interface with DDR memory. These proprietary circuits include special wiring and DLL based phase shifting for DQS gating, and the DQ data validation circuit informs the memory of the start of a read burst. When DQS gate exits and enters three states again, the pre synchronous and post synchronous detectors process DQS gate correctly, and the on-chip terminal circuit provides maximum signal integrity. Not all FPGAs have these proprietary circuits. The interface cost and complexity of high-speed DDR memory vary greatly, which depends on the specifications of FPGA family.
During the memory read cycle, the memory drives edge aligned DQ data and DQS gating signal. FPGA is allowed to acquire data with strobe signal, which must accurately phase shift 90 degrees relative to data, and then capture all data bits at the same time. Because DQS strobe signal is not a signal of free choice path, FPGA can use master-slave DLL method, master DLL latch to the system clock, and then control the slave delay line which will shift the strobe signal to 90 degrees accurately.
When the signal is transferred from FPGA to memory and then back to FPGA, the delay on the circuit board is usually unknown and varies with temperature and voltage. Therefore, the time from issuing a memory read command to effective data arriving in FPGA is uncertain. The DQ data valid circuit in FPGA can be used to monitor DQS gating and send read pulse start signal to start valid data. Usually, this requires some detection means to detect the change of strobe signal from three states to activation at the beginning of synchronization before reading pulse.
Because DDR memory uses the electrical interface of SSTL and HSTL, they terminate to half of the voltage in parallel, so the signal in the three states always floats to the domain value voltage of the input buffer. This will lead to spurious oscillation of DQ data and DQS gating signal, unless there is a special circuit to prevent this behavior. FPGA contains dual field input buffer and minimum pulse width detector to prevent DQS gating oscillation before and after read synchronization.
Ddrsram and SDRAM devices are used for the combination of various single ended and differential SSTL and HSTL electrical signals. The clock inputs of these memories are differential, so the FPGA output driver must minimize the skew between positive and negative signals. Similarly, in order to ensure the maximum signal integrity on the memory interface, FPGA with the ability of serial and parallel termination should be used to drive and receive various signals constituting the interface.
The current new generation of DDR memory system uses static parallel termination, either on the circuit board or in the memory controller chip. In order to achieve high speed and reduce the power consumption of system terminal at the same time, the new generation DDR2 uses switchable parallel terminal and control output impedance driver in memory and controller. FPGA for DDR2 applications includes these functions.
For the output part, FPGA realizes the interface between image processing and screen driver circuit through LVDS or new RSDS standard. LVDS and RSDS are low-noise, low-power, low amplitude differential signals, which are used to transmit high-speed, gigabits per second data transmission signals on copper wire. RSDS has lower voltage swing and output drive current than standard LVDS, resulting in lower EMI and power consumption, as shown in Table 1.
Summary of this paper
Choosing FPGA supporting LVDS and RSDS can put the screen driver into FPGA. In addition, system designers expect FPGA manufacturers to provide intellectual property cores and easy-to-use design tools to further reduce costs and accelerate product time to market. The Latice ecp-dspfpga series supports a variety of requirements, including RSDS, LVDS, DDR and DSP, and the programmable logic supports a variety of display standards and formats. In addition, due to support a variety of DSP intellectual property core and MATLAB Simulink, the design is more convenient.
Editor in charge: GT