-Hbm3 IP solution can provide memory bandwidth of up to 921gb / s for high-performance computing, AI and graphics SOC

Mountain view, California October 22, 2021 / AP /–

main points:

  • Designware hbm3 controller, phy and verification IP can reduce the integration risk and greatly improve the memory performance of 2.5D multi bare chip system
  • The low latency hbm3 controller with flexible configuration options enhances memory bandwidth
  • In the 5nm process, the pre hardened or configurable hbm3 PHY has an operating rate of 7200 Mbps and a data rate of up to 2x, which can improve the power efficiency by 60% compared with hbm2e
  • The verification IP and memory models for zebu and haps can provide an end-to-end solution, enabling rapid verification convergence from IP to SOC
  • 3dic compiler of Xinsi technology is an integrated multi bare chip design and analysis platform, which provides a comprehensive hbm3 automatic wiring solution and can realize rapid and robust design and development

Synopsys, Inc., NASDAQ: SNPs) recently announced the launch of the industry’s first complete hbm3 IP solution, including controller, phy and verification IP for 2.5D multi bare chip packaging system. Hbm3 technology can help developers meet the requirements of system on chip (SOC) design for high-performance computing, AI and graphics applications for high bandwidth and low-power memory. Designware of Xinsi Technology ® Hbm3 controller and PHY IP are based on silicon verified hbm2e IP, make full use of the intermediary expertise of Xinsi technology, and can provide low-risk solutions to achieve memory bandwidth of up to 921gb / s.

Xinsi technology verification solution includes verification IP with built-in coverage and verification plan for zebu ® Simulated off the shelf hbm3 memory model and haps ® The prototype verification system can speed up the verification from hbm3 IP to SOC. In order to accelerate the development of hbm3 system design, Xinsi technology 3dic compiler multi bare chip design platform provides a fully integrated architecture exploration, implementation and system level analysis solution.

Xinsi technology designware hbm3 controller IP supports various hbm3 based systems with flexible configuration options. The controller can greatly reduce delay and optimize data integrity. It has advanced Ras characteristics, including error correction code, refresh management and parity.

Designware hbm3 PHY IP adopts 5-nm process and can provide pre hardened or customer configurable PHY. The operating speed of each pin is up to 7200mbps, which significantly improves the power consumption efficiency and supports up to four effective working states, so as to realize dynamic frequency regulation. Designware hbm3 PHY utilizes optimized micro bump arrays to minimize footprint. Based on its support for the winding length of the intermediary layer, developers can arrange PHY more flexibly without affecting performance.

Xinsi technology’s verification IP for hbm3 uses a new generation of native SystemVerilog universal verification methodology (UVM) architecture to simplify the integration difficulty of the existing verification environment and support more test runs, so as to shorten the time required for the first test. The off the shelf hbm3 memory model for zebu simulation and haps prototype verification system can realize RTL and software verification, so as to achieve a higher level of performance.

John koeter, senior vice president of marketing and strategy of Xinsi technology, said: “Xinsi technology continues to meet the design and verification requirements of data intensive SOC, and provides high-quality memory interface IP and verification solutions for leading protocols such as hbm3, ddr5 and lpddr5. The complete hbm3 IP and verification solutions enable developers to rely on the same supplier to meet the increasing bandwidth, latency and power requirements, while accelerating verification convergence.”

Xinsi technology’s extensive designware IP portfolio includes logic library, embedded memory, PVT sensor, embedded test, analog IP, interface IP, security IP, embedded processor and subsystem. In order to accelerate prototype design, software development and integrate IP core into chip, Xinsi technology “IP accelerated” plans to provide IP core prototype design kit, IP core software development kit and IP core subsystem. We have invested heavily in IP quality and comprehensive technical support to help developers reduce integration risks and shorten product time to market.

Testimony of customers and partners

Mark montierth, vice president and general manager of high performance memory and network business of micron, said: “Micron is committed to providing the industry’s best performance solutions for the world’s most advanced computing systems. The memory bandwidth provided by hbm3 is crucial to the realization of the next generation of high-performance computing, artificial intelligence and megabyte systems. Our cooperation with Xinsi technology will accelerate the development of hbm3 product ecosystem to achieve unprecedented ultra-high bandwidth, power consumption and performance.”

Kwangil Park, senior vice president of Samsung electronic memory product planning, said: “In the era of data-driven computing, the development of artificial intelligence, high-performance computing, graphics and other applications has greatly increased the demand for memory bandwidth. As the world’s leading memory chip manufacturer, Samsung has been committed to supporting the formation of ecosystem and developing HBM to meet the growing bandwidth demand of all applications. Xinsi Technology is the ecosystem leader of HBM industry Drive is also an important partner of Samsung. We look forward to working with Xinsi to continue to provide customers with better HBM performance. “

Cheol kyu Park Hyun, vice president of SK Hynix, head of HBM products and DRAM Design Director, said: “As the world’s leading semiconductor manufacturer, hisilic continues to invest in the development of next-generation memory technologies, including hbm3 DRAM, to meet the needs brought by the exponential growth of AI and graphics application workload. Establishing a long-term cooperative relationship with Xinsi technology will help us provide our common customers with fully tested and interoperable hbm3 solutions to improve memory performance Energy, capacity and throughput. “

Yutaka Hayashi, vice president of data center and network business of socienext, said: “Socienext, a global leader in SoC solutions, works together with Xinsi technology, an industry-leading partner, to provide comprehensive solutions for our common customers in a wide range of markets. Based on Xinsi technology’s hbm2e IP in the 5-nm process and the integrated system wide bare polycrystalline chip design platform, our cooperation with Xinsi technology will be expanded, including the latest designware hbm3 IP And validate the solution to help our customers achieve higher memory performance and capacity in the SOC of hbm3 specification. “

Supply and resources

Xinsi technology designware hbm3 controller, phy and verification IP, zebu simulation memory model, haps prototype design system and 3dic compiler are available from stock.

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