In the high-frequency ultrasonic data acquisition system, many high-speed A / D converters can not be directly connected with the processor. At this time, FIFO needs to be used to build a bridge between the processor and the A / D converter. The first in first out characteristic of FIFO can easily cache a large number of data blocks. In the ultrasonic thickness measurement system based on arm, the high-frequency ultrasonic probe above 1MHz is used. The frequency of the measured data after a / D conversion does not match the data receiving capacity of ARM processor. Therefore, a FIFO needs to be connected between a / D and arm processing to solve the above problems. The design selects the A / D chip ad9283 of ad company and cy7c4261 of cyperss company for FIFO. The maximum sampling frequency of both is 100 MHz. Arm adopts S3C2410 processor of SamSung company. The three have strong external interface capability, which is convenient for seamless connection, simple hardware interface circuit and convenient debugging.
1 chip selection
1.1 S3C2410 processor
S3C2410 processor is Samsung’s ARM920T processor core based on ARM company, which adopts 0.18 μ M 32-bit microcontroller for manufacturing process. The processor has: independent 16 KB instruction cache and 16 KB data cache, MMU, LCD controller supporting TFT, NAND flash controller, 3-way UART, 4-way DMA, 4-way timer with PWM, I / O port, RTC, 8-way 10 bit ADC, touch screen interface, I2C-bus interface, iis-bus interface, 2 USB hosts, 1 USB device, SD host and MMC interface, 2-way SPI. S3C2410 is a 16 / 32-bit RISC architecture processor. It uses the powerful instruction set of ARM920T CPU core. The processor can run at 203 MHz at most.
1.2 ad9283 high speed analog-to-digital converter
In ultrasonic nondestructive testing system, the frequency of ultrasonic probe is generally 2 ~ 10 MHz. The probe frequency is 5MHz. According to the sampling theorem, the sampling frequency is preferably 5 ~ 8 times of the probe frequency. Therefore, the A / D chip adopts ad9283 of ad company, and its maximum sampling rate is 100MHz, which can meet the system requirements.
1.3 FIFO memory cy7c4261
As a bridge between a / D and arm, the parameters of FIFO memory directly affect the data acquisition speed. Firstly, the read / write speed of FIFO memory should be fast enough. In order to facilitate debugging, it is best to be consistent with the maximum speed of a / D device; Secondly, the storage capacity of FIFO memory should be appropriate. If the capacity is too large, it will cause a waste of resources. If the capacity is too small, it will cause overflow or slow data acquisition speed.
The thickness of the commonly used measured object is 10mm. When the signal length takes the first 8 peaks and the whole system works at the limit frequency of 100MHz, the following calculations are made:
Number of samples = sampling rate × time
=Sampling rate × （2 × thickness × 8 / ultrasonic speed)
That is, nearly 3 KB of cache is required. The ultrasonic thickness measurement system needs to measure objects with a thickness of 50 mm at most, so it needs a capacity of 15 K × 8 B FIFO. Therefore, the depth of FIFO should be greater than 15 KB; The number of bits with width greater than a / D, i.e. greater than 8 bits; The maximum operating rate is 100 MHz, which is consistent with the A / D sampling rate. The design selects the FIFO memory cy7c4261 of CY company, and its maximum sampling rate is 100 MHz, which is the same as that of ad9283; 16 KB capacity × 9 B, which can meet the data volume requirements.
2 interface design
Ad9283 is an 8-bit A / D converter, cy7c4261 is a 9-bit FIFO, and the data bus of S3C2410 is 32 bits. Cy7c4261 only needs to be connected to the low 8-bit do ~ D7 of S3C2410. Due to the FIFO structure, the system does not need any address line to participate, which greatly simplifies the circuit. The data obtained from a / D sampling should be sent to FIFO in real time. The write clock frequency of both must be the same, and the minimum clock input of ad9283 and cy7c4261 is 10 ns, which is unified and convenient to operate. 74als08 is a four two input and gate. Toutl (gpbl) and tout2 (gpb2) in the PWM wave output port of arm are configured as general output ports to control the on-off of 74als08, so as to control the write clock of a / D and FIFO. Clkouto of S3C2410 is connected with rCLK of cy7c4261 to provide read clock for FIFO. The full flag bit FF of cy7c4261 is connected with the external interrupt eintl of S3C2410 to trigger the external interrupt. Nrstoutl of S3C2410 is connected with RS of cy7c4261 to reset FIFO. The interface block diagram is shown in Figure 1.
3 timing design
The write clocks of a / D and FIFO are controlled by two and gates respectively. Because the ad9283 needs 4 clock cycles from the analog input to the converted data on the output port, and the delay effect of the wire will be very obvious when sampling at high speed. If the clocks of a / D and FIFO are connected together, it is likely to collect too much invalid data. After separate control, the clocks of a / D and FIFO can be controlled conveniently through software delay. Debugging is quite convenient, trying to minimize the number of bits of invalid data. The working sequence of ad9283 is shown in Figure 2, and the writing sequence of cy7c4621 is shown in Figure 3.
When sampling. Enable toutl through the program, and the output of tout2 is 1. At this time, the sampling clock pulse is connected with toutl and tout2 and sent to the clock input encode of ad9283 and the write clock input wclk of cy7c4621 respectively. At this time, the A / d starts to work, and the A / D sends the conversion data to its own output ports d0 ~ D7. When the write enable Wen1 is low and Wen2 is high, the data on the A / D output port is sequentially written to the FIFO on the rising edge of wclk. A / D and FIFO will complete a / D conversion and store the data in FIFO in sequence. The maximum data storage capacity of cy7c4261 is 16 KB. After 16 KB conversion, cy7c426l cannot store new data. At this time, the memory full flag FF outputs low level (high level when not full). Connect this signal to the external interrupt eintl of S3C2410 and use it to generate an interrupt from high to low to indicate that a group of data acquisition is completed.
In the interrupt, arm first quickly turns off the output of sampling pulse signal (toutl and tout2) to 0 and stops the work of a / D and FIFO. The external clock signal clkouto of arm is connected with the read input rCLK of FIFO. Clkout0 sends a pulse to rCLK every time arm performs I / O read operation. Set the FIFO reading to enable Wen1 and Wen2 to be low, and continuously perform 16K I / O reading operations at the same time, and the data will be sent from cy7c4261 to S3C2410 system in turn. The whole data acquisition work is completed. Before each data acquisition, reset cy7c4261, configure nrstoutl of s3c24-10 as a general output port, and input a low pulse of no less than 10 ns to RS pin of cy7c4261, that is, output a low pulse at nrstoutl pin of arm. This can more fully ensure the stability of FIFO read and write pointers.
4 data acquisition process
The data acquisition workflow of ultrasonic thickness measurement system mainly includes arm initialization, input excitation pulse, enable external interrupt, clock sending to a / D, FIFO and waiting for interrupt. Stop a / D and FIFO, arm reads data and resets FIFO. The flow chart is shown in Figure 4.
Through practical design, in the ultrasonic nondestructive testing system based on arm, FIFO can make a good seamless connection between high-speed A / D and arm processor, and solve the problem of mismatch between them. Through software setting, the operation sequence of a / D, FIFO and arm can be flexibly adjusted, and the debugging is simple, which ensures the safety and reliability of data acquisition. The interface circuit is simple, flexible and efficient, and has high application value.