With the faster and faster rate of modern high-speed signal, the steeper and steeper signal edge, the further reduction of chip power supply voltage and the increase of clock frequency and data reading rate, it is required to consume more power. While analyzing and studying the signal integrity of electronic system, how to provide stable and reliable power supply to electronic system has also become one of the key research directions. At present, the analysis method and practice of power integrity engineering are still in the stage of continuous exploration. Using simulation technology, under the overall scheme and design criteria that meet the processing, manufacturing and testing conditions, the power integrity problem can be solved as much as possible in the early stage of product design, which can minimize the product cost and shorten the R & D cycle. At present, some EDA tools provide corresponding power integrity (PI) simulation and analysis functions. Allegro provides a good interactive working interface and is closely combined with its front-end products cadence, Orcad and capture, providing the most perfect solution for the current high-speed, high-density and multi-layer complex PCB design. This paper uses cadence PI in Allegro to analyze the power integrity of ARM11 core system, and tests the power integrity of PCB to verify the results of simulation analysis.

1 theoretical analysis of power integrity

1.1 concept of power distribution system

In the electronic system, the function of the power subsystem is to provide stable voltage reference and sufficient driving current for all devices. Therefore, there should be low impedance power connection and grounding connection between the power circuit and the functional circuit. An ideal power supply system has an impedance of 0 and the potential at any point in the plane is constant, but the actual power supply system has complex parasitic capacitance and inductance, and the power supply voltage provided by the power supply chip is not an ideal constant value.

Power distribution system (PDS) is composed of target impedance, voltage regulator module (VPM), power / ground plane, decoupling capacitor and high-frequency ceramic capacitor.

The power integrity problem refers to that the power distribution network in the high-speed system has different input impedance at different frequencies, resulting in voltage jitter △ V caused by noise current △ I and transient load current △ I ‘on the power / ground plane. This voltage fluctuation, on the one hand, affects the plane to provide a stable voltage reference for digital signals, on the other hand, it will jitter the supplied power supply voltage and affect the working performance of the device. When the plane voltage fluctuation exceeds the tolerance range of the device, the system will not work normally. The key to the design of power distribution system is the target impedance Z, which is defined as equation (1):

Where VDD is the chip power supply voltage, ripple is the allowable voltage fluctuation of the system, and △ IMAX is the maximum transient current change of the load chip. The purpose of the power supply system is to provide sufficient driving current with a constant voltage value within a limited reaction time, so it is necessary to have a sufficiently low power supply impedance.

1.2 solutions to power integrity

Voltage regulation module, power / ground plane, decoupling capacitor and high-frequency ceramic capacitor play a decisive role in the impedance of power distribution system in different frequency ranges. In the low frequency band from 1kHz to several Hz, the voltage regulator adjusts the output current to adjust the load voltage; In the intermediate frequency band of several MHz to hundreds of MHz, the power supply noise is mainly filtered by the decoupling capacitor and the power / ground plane of PCB; In the high-frequency part above 1 GHz, the power supply noise is mainly filtered by the power / ground plane of PCB and the high-frequency capacitor inside the chip. When doing Power Integrity simulation, the really meaningful frequency band is mainly in the frequency band of several MHz to hundreds of MHz. At present, there are mainly two ways to solve the problem of power integrity:

One is to optimize the stack design and layout of PCB. In high-speed PCB design, the whole copper layer is usually used as the power / ground plane to reduce the input impedance as much as possible. The power supply and ground plane can be regarded as a planar capacitor, especially in the low intermediate frequency stage, the equivalent series resistance and equivalent series inductance are very small, and have good decoupling filtering characteristics. Integrating the impedance matching made by the previous signal integrity and the current production standards, reasonably setting the interlayer spacing and selecting the appropriate inter board capacitance value can well improve the power integrity of high-speed design. The capacitance values of power supply and ground plane can be estimated as equation (2):

Where, ε o=8.854 pF; ε R = 4.5 (FR-4 material calibration value); A is the copper laying area of power supply layer (M2); D is the interval between copper laying power layers (m). According to the simulation results, the smaller planar capacitor C has higher impedance response curve and higher resonance frequency.

The second is to arrange decoupling capacitors. This is the most effective way to solve the problem of power integrity. In the high frequency system, the parasitic inductance in the power distribution system can not be ignored, which directly leads to the increase of the impedance of the power distribution system. Because capacitance and inductance have opposite characteristics in frequency domain, the method of adding capacitance can be used to reduce the increase of impedance caused by inductance. At the same time, the capacitor has energy storage effect and can respond to the changing current demand at a very fast speed, so it can effectively improve the transient response ability of the power supply in the local area. How to select the appropriate capacitance and determine the appropriate placement position of the capacitance so that the impedance of the power distribution system is less than the target impedance in the whole working frequency range of the PCB system has become the key to solve the problem of power integrity. With cadence PI, the capacitance, quantity and placement position of decoupling capacitors can be quickly determined to improve development efficiency.

2 Power Integrity simulation

2.1 ARM11 core system

In this paper, cadence Pi is used as the simulation tool to analyze the power integrity of ARM11 core system. The ARM11 core system in this paper adopts S3C6410 chip. S3C6410 is an ARM11 architecture, FBGA package and a chip that needs multiple power supplies. In this paper, the chip has two working voltages: core power supply 1.2 V, 26 power pins (10 core power pins, 16 logic power pins); The input / output interface is powered by 3.3 V and has 30 I / O power pins. The internal working frequency of the chip is 667 MHz, and the working frequency of the external memory input / output interface is 266 MHz. ARM11 core system adopts 8-layer laminated structure, and the inter layer spacing is set on the premise of signal simulation impedance matching and production standards. In this paper, cadence Pi is used to analyze the core voltage power supply network VDD of ARM11_ Arm for Power Integrity simulation.

According to the S3C6410 chip data manual, the core current consumption is 200 Ma, plus 100% tolerance, the allowable voltage fluctuation value of the system is 4%, and the core voltage is 1.2V. According to equation (1), the target impedance is set as 0.12 Ω in the simulation.

2.2 Power Integrity simulation

2.2.1 single node simulation, analysis, verification and optimization of capacitor selection

In the single node simulation, the actual physical connection of each component in the power system is ignored. Assuming that the power voltage regulation module VRM, simulation excitation source, current source and all capacitors are connected in parallel, the capacitance required to maintain the target impedance can be obtained in the single node simulation.

2.2.2 multi node simulation, place decoupling capacitors and optimize the layout

Since the layout of decoupling capacitor is not considered in single node simulation, in order to obtain more accurate results, multi node simulation is carried out in the full frequency range considering the noise source and the placement position of decoupling capacitor. In multi node simulation, cadence PI divides the power plane into multiple grids according to user definition, models each grid, and then connects the placed decoupling capacitor, voltage regulation module VRM and noise source with specific grid points to generate the frequency impedance simulation waveform of each node.

In order to obtain high accuracy, the grid size must be greater than 1 / 10 of the wavelength corresponding to the highest frequency of the system.

2.2.3 static IR drop DC voltage drop analysis of power plane

In order for the chip to work normally, the power supply voltage needs to be limited within the allowable fluctuation range. Power fluctuation is caused by DC loss and AC noise. DC voltage drop DC IR drop is the main cause of DC loss. Static IR drop DC voltage drop is mainly related to the width and layer of metal wiring, the current flowing through the path, the number and position of vias. After setting the power supply pin and current filling in cadence PI, the ARM11 core power supply voltage network VDD after layout and wiring is completed_ Arm conducts DC voltage drop analysis. When the working frequency of ARM11 core system is 667 MHz, the allowable fluctuation range of 1.2 V DC voltage is + / – 0.05 v. VDD is calculated by cadence PI simulation software_ The arm network voltage gradient, in which the maximum value of drop is 0.013 V, which is + / – 0.05 V less than the allowable fluctuation, fully meets the working voltage requirements of S3C6410 and can ensure the stability of the system.

2.2.4 power plane current density analysis

When there are too many vias on the power plane or the distribution is unreasonable, the current will flow through the narrow area, resulting in excessive current density in the area. The area with the largest current density on the power plane is called hot spot, which may lead to serious thermal stability problems. Therefore, vias should be designed reasonably to make the current density distribution of the board uniform and avoid hot spots near key chips and high-speed wiring.

3. PCB Power Integrity Test

In version 1 PCB, cadence PI analysis is not used, but some decoupling capacitors are placed according to experience. During debugging, it is found that the waveform of high-speed digital signal is not good, and sometimes there are bit errors. In the second edition, the numerical quantity and position of decoupling capacitor and the layout and wiring of some components were adjusted through cadence PI analysis.

The switching power supply 1.2 V provides 0.5 V for the power plane_ The output current is about 2 ~ 0.8A. When the dynamic load is at constant voltage, the output impedance changes periodically, and the current amplitude can complete the jump of 0.2 ~ 0.8A in the same period. It can be seen from the data that after cadence PI analysis, the power integrity of the 2nd PCB produced has been greatly improved.

4. Conclusion

After the simulation analysis of cadence PI, the PCB board of ARM11 core system is made. Through the actual measurement of the circuit, it is found that each power distribution system can work well, which is basically consistent with the simulation results. With the rapid increase of system frequency, the complexity of power distribution system and the strict control of engineering production cost and cycle, it is necessary to carry out Power Integrity simulation analysis and simulate the behavior of real system at the system level in the design of electronic system, so as to improve design efficiency and reduce design error.