In FPGA, if we want to convert a signal with sampling rate of 480mhz and if frequency of 302.5mhz to baseband signal with zero if, what should we do?

First of all, the sampling frequency of 480mhz can only be band-pass sampling for a signal with an intermediate frequency of 302.5mhz. After sampling, the actual frequency of the signal is 177.5mhz. Then, DDS should be used in FPGA to generate a carrier signal with a frequency of 177.5mhz. If the clock frequency is at least twice that of 177.5mhz, that is 355mhz, the clock frequency is too high, which is easy to cause timing problems later We can try to use the idea of area for speed to reduce the working frequency of the clock. We decided to make the clock work at 120mhz, which is more stable.

If the clock works at 120mhz, the signal with the sampling rate of 480mhz at the beginning will be converted into four channels in series and parallel. Each channel has a sampling rate of 120mhz, and the sampling rate of 120mhz samples a 177.5mhz IF signal, so the signal frequency has actually changed to 57.5mhz. Therefore, at this time, the downconverter shall be used for 4 channels of 57.5mhz signals respectively, but the initial phase of DDS generated signal shall be noted. Originally, when the sampling rate of 480mhz is 1, 2, 3, 4, 5, 6, 7, 8, the corresponding signal of each channel is 1, 5; 2, 6; 3, 7; 4, 8, then the 4 channels of 57.5mhz signal generated by DDS should also be corresponding. How to use DDS of FPGA to generate 4 corresponding carrier signals is described in detail below.

So how can we use the clock frequency of 120mhz to generate a carrier signal with a frequency of 177.5mhz? The sampling rate of 120mhz can generate a signal with a frequency of 177.5mhz. In fact, the signal frequency has changed to 57.5mhz. If the four-way carrier is to be multiplied by the previous signal, how much should the initial phase difference between the signals be?

If a 177.5mhz signal is generated at a sampling rate of 480mhz, the phase difference between each adjacent two points is (177.5 / 480) x 2 * PI, then when setting DDS in FPGA, the initial phase of the first signal is 0, the second signal is (177.5 / 480) x 2 * PI, the third signal is (177.5 / 480) x 2 * pi * 2, and the fourth signal is (177.5 / 480) x 2 * pi * 3-2 * PI.

Then multiply the above 4 channels of DDS carriers with the previous 4 channels of signals respectively, and then use multiple filters to extract the 4 channels of signals. How to use multiple filters to extract the 4 channels of signals can refer to my previous article. This completes the down conversion and down sampling in the signal preprocessing, which is also the most common signal processing function to be completed in FPGA. Because the signal sampling rate is too high, we have to use the area for speed processing method to complete this function.