In embedded system, low power design is a problem that must be faced in the process of product planning and design. Semiconductor chip performance doubles every 18 months. But at the same time, battery technology can not keep pace with the pace of semiconductors, and the capacity of a battery with the same volume can only double in 10 years. Embedded system for the use of time and standby time requirements are also higher and higher, which requires the design of products in full consideration of the whole system of low-power design. Power control is a systematic project, which needs to be considered from the aspects of low-power device selection, low-power design and manufacturing technology of hardware, and low-power optimization of software. Based on the projects that the author has served in Runxin science and technology, the author summarizes the design points of low power consumption of embedded system from the above aspects.

With the continuous development of semiconductor technology, semiconductor manufacturing technology is also in continuous progress, the use of advanced technology and low-power design components can reduce the power consumption of the whole system from the source. The selection of master chip should fully consider the use scenarios of the system. For those application scenarios with more computing tasks, chips with high energy consumption ratio can be selected for design, such as Apollo series chips of ambiq. The chip adopts the patented spot technology, and the chip operates stably in subthreshold, which can reduce energy consumption by nearly 13 times and realize the ultimate low-power technology.

For embedded system, power chip is an important device for low power design. The power consumption and conversion efficiency of the power chip greatly affect the battery life. Low power LDO or DCDC chip is needed to design low-power regulator circuit, such as TI’s tps797 series, which consumes only 1.2ua.

How to realize low power design in embedded system

In the case of meeting the functional requirements, try to choose the external devices with trigger output function instead of those requiring polling, so as to reduce the running time of MCU. Usually, the MCU can be in sleep state all the time. When the trigger conditions are met, the external devices wake up the MCU through interruption. Hardware design is also very important for the power consumption of embedded system.

For those peripherals that do not need to work in low power consumption mode, MOS transistor circuit and MCU control can be used to manage the power of local circuits. When the device does not need to work, try to turn off the part of the power supply to achieve lower power consumption.

In multilevel voltage design, voltage and power consumption are closely related. Therefore, to reduce the power consumption, different voltage levels can be used for different circuit modules. Dvfs dynamic voltage and frequency technology can be used to reduce the power consumption of different circuit modules in the system in real time by reducing the working voltage and frequency of different circuit modules to just meet the minimum requirements of the system. The hardware design should avoid leakage current of IO port for each IO port of MCU. When the peripheral device is powered down, the IO port will still have potential power output, so the IO port needs to be configured as low level or high level by default to avoid leakage current.

Software optimization of power consumption involves many levels and aspects. Properly reducing the CPU operating frequency and MCU running speed can effectively reduce the current consumption during operation. The power consumption of the chip is linear with the main frequency. Higher clock frequency means faster MCU running speed, so the switching frequency of the internal CMOS circuit in MCU will be faster, resulting in higher operating current and standby current.

Reasonable use of MCU standby mode, when there is no task to be processed, the MCU will be put into low-power sleep mode. For embedded products that use embedded operating system, usually they enter sleep mode in idle task. However, in order to further reduce power consumption and achieve optimal design of low power consumption, we can not directly put sleep or shutdown mode on idle tasks. We need to design a more advanced sleep mechanism, such as using tick in FreeRTOS operating system In the less low-power mechanism, after entering the idle task, the maximum time that can execute the low-power consumption should be calculated first, that is, how much time is left for the next high priority task to be executed. After that, the system will wake up from the low power consumption mode and continue to perform multi tasks.

Pay attention to the level status of each GPIO port, and configure all GPIO ports to high level or low level before sleep to reduce leakage current. For external sensors and peripherals, the power consumption mode should be configured before sleep to reduce the current consumption.

It is important to turn off the internal power consumption of the deep / analog module as soon as possible, and the key point is to turn off the power consumption of the analog module as soon as possible. In addition, due to the continuous refresh of SRAM in the chip, it also needs to consume a certain amount of current in sleep mode. Some SRAMs can be configured to keep refreshing in sleep mode to reduce power consumption.

For the standby chip, there are reasonable configuration parameters to reduce the power consumption. For example, for ble chip csr1010, in the broadcasting mode of ble, the standby current of 60ms broadcast interval is 394a. If the broadcasting time is increased to 1.28s, the standby current is reduced to 28a. For WiFi chips, such as the high pass qca4004 chip, the corresponding power consumption is 1.5mA in dtim1 and 334A in dtim10.

Low power consumption of embedded system requires comprehensive consideration of various possible factors, conditions and states, careful consideration and analysis of various details, calculation and analysis of various possible schemes and methods are required, and the power consumption of the whole system is optimized as much as possible to achieve the purpose of saving power.


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