introduction

There are two ways to implement in-application programming (In ApplicaTIon Pro-gramming, IAP) in FPGA: one is to add external circuits on the circuit board. For example, use MCU or CPLD to receive configuration data, program FPGA or Flash device (including EPCS and Flash) by external circuit in passive serial (PS) mode, and then control the configuration reset pin of FPGA to reset the entire FPGA, and finally The FPGA uses the master serial method to configure itself. The other is to receive programming data through the Nios CPU or dedicated IP in the FPGA, program the Flash chip, and then reset and start the FPGA through an external simple circuit to configure in active serial (AS) mode.

In order to reduce the area of ​​the circuit board, save the cost and improve the reliability, the second method is adopted in this design. The requirements of this design are: the hardware circuit must be configured as an active serial mode, that is, select MSEL[1:O] as l:O; with EPCS, or with EPCS and Flash at the same time; with the function of communicating with the PC. The FPGA receives the updated data, stores it in the Flash device, and then resets the Nios or FPGA to update the hardware and software.

1. System hardware design

The system is mainly composed of Cyclone FPGA, EPCS, Flash and serial communication. The hardware structure is shown in Figure 1.

EPCS adopts Altera’s EPCS4, with a capacity of 4 Mb, fewer pins, low cost, and support for 3.3 V low-voltage operation. The Flash chip adopts AMD’s Am29LV640MH/L and supports 3. OV low-voltage operation, with low power consumption, the chip capacity is 64 Mb, which meets the storage of large-capacity data; parallel port operation, fully compatible with Cyclone FPGA, and there is a corresponding CFI_FLASH core in SOPC, which is convenient for hardware circuit design .

2. Working principle

2.1 Several concepts

FPGA configuration data: it is a sof file, the sof file is programmed into the Flash, and the FPGA can be configured from the Flash after power-on. The sof file is the basis of other configuration files, and other files can be converted from the sof file.

Software data: Create an elf file through NiosII IDE, program the user program into Flash, and allow the software program to be loaded from F1ash after reset, thereby starting the NiosII CPU.

2.2 Programming files

The programming file is a file in Flash format, namely S-reeorld (referred to as “SREC”) format. The SREC format is a programming format standard developed by Motorola. The SREC format file is composed of a group of ASCII codes, all hexadecimal data are in uppercase form, the structure description is as follows:

①Start code. Start with S as a data line.

②Record type. A decimal number (O to 9), which defines the type of the data field.

③Number of bytes. 1 byte, which defines the number of bytes other than the address byte and check byte after the number of bytes.

④Address. Consists of 4 (or 6, 8) bytes that define where the first data byte is stored.

⑤ Data bytes. It consists of n bytes, and the data byte is the actual and effective programming information.

⑥ Check byte. 1 byte, used for verification, all hexadecimal bytes are added to take 8 bits, which is 0xFF.

2.3 AS configuration mode

The configuration data of the FPGA is stored in internal SRAM cells. Since the data will be lost after the SRAM is powered off, the configuration data must be rewritten into the SRAM each time it is powered on. This process is called “FPGA configuration”. It can be seen that the configuration information of the FPGA is stored in the internal RAM of the FPGA. It can be seen that in the active serial mode, the FPGA reads the configuration data from the EPGS and stores it in the internal RAM.

AS configuration mode supports StraTIxII and Cyclone series FPGAs. By configuring MSEL[1:O] to 1:0, select active configuration mode (except JTAG mode that is not controlled by MSEL, other configuration methods are determined by MSEL). AS configuration mode uses serial configuration devices (EPCS1/EPCS4/EPCSl6/EPCS64). In the AS configuration process, the FPGA of StraTIxlI and Cy-clone series is the master device, and the serial configuration device is the slave device. As shown in Figure 2, in AS configuration mode, the FPGA receives configuration data through DATA0, and the configuration data and DCLK are synchronized. 1 bit of configuration data is transferred every clock cycle. The configuration process is represented by controlling nCONFIG, nSTATUS, CONF_DONE. The serial configuration chip latches the input signal and control signal at the rising edge of DCLK, and outputs the configuration data at the falling edge. The Cyclone chip outputs the control signal at the falling edge of DCLK and latches the configuration data.

3. Workflow

3.1 Update of hardware configuration

As shown in Figure 3, the configuration process of FPGA is divided into: reset, configuration and initialization.

(1) Reset the FPGA

Power-on reset: In user mode, when the nCONFIG pin remains low for 40 μs, the FPGA will enter the reset state. During reset, the FP-GA samples the level value of the MSEL pin to determine the configuration method used; at the same time, the nSTATUS and CONF_DONE pins are set to low level by the FPGA, all I/0 pins are tri-state and the FPGA is internally configured registers are cleared.

2 methods of FPGA reset:

①Add RC reset circuit or reset chip to automatically generate power-on reset pulse.

② Refer to the chip manual. If the chip provides a power-on reset pulse (usually a global reset signal), use it as a reset signal; if not, check whether the chip gives the default value of the register unit power-on (usually O), and use this feature to reset Or generate a reset pulse.

(2) Configure FPGA

After reset, nCONFIG is pulled high by an external pull-up resistor to enter the configuration stage. At this point, nSTATUS is released by the FPGA and pulled to a high level by an external pull-up resistor to enter the configuration state. The Cyclone chip enables the serial configuration chip by setting the signal output by nCSO low. The nCS0 pin is connected to the chip selection section (nCS) of the configuration chip, and the serial clock (DCLK) and serial data output (ASDO) pins are used to transmit Operation commands, and/or read address signals into the serial configuration chip. Then configure the chip to send the data to the serial data output (DATA) pin, and the DATA pin is connected to the DATA0 input pin of the Cyclone chip. Configuration data is loaded into the FPGA on the rising edge of the DCLK clock. When all configuration bits are received (CRC check is correct), the Cyclone chip suspends the CONF_DONE pin, which is pulled up by an external 10 kΩ resistor; at the same time, it stops driving the DCLK signal. The initialization starts only after CONF_DONE reaches a certain logic high level.

(3) Initialization stage

In the Cyclone chip, the initial clock source is the lOMHz (typical) internal crystal oscillator of the Cyclone chip, or the optional CLKUSR pin. The internal crystal oscillator is the default initialization clock source. If the internal clock is used, the Cyclone chip provides enough clock for proper initialization. The advantage of using the internal clock is that it is not necessary to send other clocks from the outside to the CLKUSR pin during initialization, and the CLKUSR pin can be regarded as an I/O pin.

(4) User mode

After initialization, the FPGA enters user mode. In user mode, user I/O pins no longer have weak pull-up resistors, but instead perform the functions assigned in the design. Cyclone chips can start reconfiguration by pulling nCONFIG low. nCONFIG low signal should last at least 40μs. When nCONFIG is pulled low, the Cyclone chip is reset and enters the reset phase. The Cyclone chip also pulls down nSTATUS and CONF_DONE, and all I/O pins are in three states. Once nCONFIG returns to logic high, the Cyclone chip will release nSTATUS and restart configuration.

(5) Errors in configuration

If an error occurs during configuration, the Cyclone chip will set the nSTA-TUS signal low to indicate a data frame error, and the CONF_DONE signal is low. If the Auto-restart configuration aftererror option is selected in the General item of the Device&Pin OpTIons window of the Quartus software, the Cyclone chip will reset by activating nCSO, release nSTATUS after the reset failure time (40μs), and try the configuration again. If this option is not selected, the external system must monitor the nSTA-TUS signal for errors, and then pull the nCONFIG signal low for at least 40µs to reconfigure.

The computer establishes a connection with the Nios program on the target board, and transmits the Flash file to the FPGA through the communication interface; after the Nios program determines the target of the transmitted file, the programming data is stored in the EPCS or Flash. The received data is first temporarily stored in SDRAM instead of directly operating on EPCS and Flash. The advantage of this is that once the transmission fails or aborts, the data in the original EPCS and Flash will not be destroyed.

When generating a Flash file through the sof2Flash command, you can open the NioslI command shell through SOPC Builder, and use the “sof2 Flash-epcs-input=”input file name.sof”-output=”output filename.Flash”” command, the generated Flash The file exists in the project directory. You can also copy the sof file to “<quartus installation directory>\kits\nios2_60\examples”, directly open the NiosII command shell, and use “sof2Flash-epcs-input=”input file name.sof”-output=”output file name .Flash&gt;”, the generated Flash file exists under “<quartus installation directory>\kits\nios2_60\examples”.

3.2 Software program update

As mentioned earlier, software programs can be stored in either Flash or EPCS. The easiest way to generate software Flash files is to compile the system under the NiosII IDE environment, and the generated Flash files exist in the directory of “Target Project”\software\debug\”Software Project”\Debug\obj\”.

Nios programs can be stored in Flash and run in SDRAM or On-chip RAM (hereinafter collectively referred to as “RAM”). In this case, a special Bootloader is required. The file exists in the “quartus installation directory”\kits\nios2_60\components\altera_nios2” directory, and the name is “boot_loader_cfi.srec”. It moves each program segment stored in Flash to the real position of each segment when the program is executed.

As shown in Figure 4, the Bootloader code is located at the low address of the Flash, and NiosII is reset by the reset circuit in the logic, and starts executing the code from the reset address. If the reset address is set in the Flash, the Bootloader code in front of the Flash will be run first after the reset, and the Bootloader code will guide the subsequent user program to the specified location. Executing the elf2Flash application will insert a Boot-copier program before the elf file, provided that the elf will be linked to run in RAM.

The workflow of Bootloader is shown in Figure 5.

NiosII C programs need to do some initialization work before running. If the program runs directly from Flash, Crt0. S is the first executed code; if the program is not run directly from Flash, then Crt0. S is the code that is first executed after the Bootloader is executed.

CrtO should still be executed after running Bootloader. s, but at this time Crt0. There are some differences between the process of s and the direct operation of the program in Flash: it does not initialize the instruction Cache, nor does it attempt to load other segments, these steps have been completed in the Boot-loader. The program image already contains these sections, and the corresponding sections (.rodata section, .rwdata section, and .exceptions section) are loaded when the program image is moved. The program image does not contain . bss segment and stack, so it still needs to be cleared. bss segment, and set stack pointer sp and global pointer gp. Bootloader does not read and write memory data, so there is no initialization data Cache, so Crt0. S still needs to initialize the data cache. As shown in Figure 6, when the Bootloader reads L, L=0 indicates that all the previous program records have been processed. This is the last program record, so it directly jumps to address A for execution. Obviously A must be the entry address of the program. If L=Oxffffffff (ie – 1), then ignore A and stop, so even an EPCS with only FPGA configuration data and no program is safe. When an EPCS has only configuration data but no program, sof2Flash will add 4 bytes of Oxff at the end of the configuration data, so that the Bootloader will not malfunction. The workflow of Bootloader is the same as that in Flash, as shown in Figure 5.

4. Software programming

Altera Corporation provides two types of functions to customers: SimpleFlash Access (simple Flash access), and Fine-GrainedFlash Access (fine-grained Flash access). This article uses the Fine-Grained Flash Access function, although it is a little more complicated than Simple Flash Access, it can avoid the usual cross-block erase problem. Because Flash is organized in blocks, an entire block is usually erased at a time. If the address written to the Flash does not match the organization of the Flash block, such as across the edge of the Flash block, the rest of the data may be erased. When using the read and write functions of Flash, the header file should contain “sys/alt_Flash.h” and “sys/alt_Flash_dev.h”, these two header files provide the driver interface for accessing the Flash device.

Flash must be opened before use. Open Flash, just like a C program opens a data file on the hard disk. Here Flash is opened using alt_Flash_open_dev() which returns a handle. E.g:

Among them, fd is the handle returned by alt_Flash_open_dev(); offset is the offset relative to the Flash base address, which is the address of the first byte of data to be read in the read operation; length is the data length of this operation, in words Festival. When the return value is, the read operation is successful.

Among them, fd is the handle returned by a1t_Flash_open_dev(); offset is the offset relative to the Flash base address, which is the address of the first byte of the data to be written in the write operation; length is the data length of this operation, in units of byte. When the return value is O, the write operation is successful.

Don’t forget to close the Flash after use, just like to close the data file after reading and writing the hard disk. Its prototype is as follows:

void alt_Flash_close_dev(alt_Flash_fd*fd);

where fd is the handle returned by alt_Flash_open_dev().

Editor’s Note: Flash device read and write procedures are omitted.

Epilogue

At present, in the development process of FPGA, each time the program is debugged and updated, the product needs to be directly connected to the computer for online operation, which limits the scope of program debugging and updating. And FPGA-based in-application programming technology is designed to break this limitation. In the application programming technology, the hardware requirements are extremely low. As long as the FPGA is Cy-clone series, has Flash devices, and has the communication capability of the upper and lower computers, it can be realized in application programming without adding too many hardware resources. If the product has network function or wireless function, it can avoid the trouble of repeated disassembly and debugging in the harsh industrial field and field. For confidential products, this technology can protect intellectual property rights and update the software and hardware of products through the network, which increases the difficulty of being cracked during the update process.

Responsible editor: gt

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