There is a core problem in the manufacturing method of integrated circuit (IC). Unless the layout designer carefully manages it, it may destroy the circuit in the manufacturing process.

IC is manufactured using iterative construction process; Many different material layers are deposited on silicon substrates to create devices and wires for circuits. Each iteration of the process deposits a thin layer of new material, which is then removed by masking and etching, leaving the desired pattern. In most modern processes, etching is completed by plasma etching process.

The silicon wafer is kept in an environment close to vacuum, and then a gaseous etchant (usually fluorine compound) is introduced into the chamber. By exciting atoms with radio-frequency radiation, the gas is excited and becomes a plasma. Plasma produces “free radicals”, a highly active compound that lacks valence electrons. The vacuum chamber also includes an electrode; The ground electrode is connected to the etched wafer. An alternating potential is applied between the electrodes, and the ion current pushes the free radical to the surface of the wafer. Free radicals react with the surface material and etch it away.

poYBAGFMMh2ATl2_ AABo9JlgtMw302. png

Figure 1 plasma etching promotes a highly oriented process. Source: pulse

Compared with wet etching, one of the main advantages of plasma etching is the ability to obtain a highly oriented (anisotropic) etching process. Deep grooves with nearly vertical sides can be etched on the wafer surface to create the incredible fine structure of modern IC.

The problem with plasma etching is that it will destroy the IC during its device construction. Ions formed in the plasma transfer charge to the etched wafer. With the establishment of the circuit layer, in some cases, the long metal track is only connected to the gate of the MOSFET. These long orbits collect charges from the plasma, which cannot “escape” to the substrate through the gate oxide. The oxide layer is usually only a few molecules thick. If enough charge is accumulated, the thin oxide layer will decompose, damage or even completely destroy the MOSFET.


Fig. 2 charge accumulation in IC leads to antenna effect. Source: pulse

This charge accumulation is often misleadingly referred to as the antenna effect. In the simulation design, we are not only worried about the complete failure of the device due to the antenna effect, but also worried about its impact on the device matching. If one of the devices is slightly damaged during manufacturing, the carefully matched devices in the current mirror and differential pair may be unbalanced.

Each connection on the IC connects the diffusion contact of one device to the gate of another device. In fact, multiple diffusion contacts are usually connected to multiple gates, but the problem still exists. During the manufacturing process, if part of the metal wiring is connected to the grid instead of the diffusion contact, this “floating” metal will collect charge from the plasma. The manufacturing rule of antenna effect is usually expressed as the ratio of floating metal area – charge collection area – to grid area. A larger charge collection region will allow more charge to be collected on the gate, making it easier to breakdown the oxide.

To prevent the antenna effect from damaging your circuit, you need to reduce the floating metal / grid area ratio or let the charge dissipate to the ground in a safe way to avoid its accumulation and damage.

In order to reduce the floating metal / gate area ratio, the layout designer must change the wiring so that the highest part of each connection is close to the gate. This will mean full connection to the diffusion contact before the floating metal area becomes too large. Sometimes this can be done naturally by completing the connection to the grid on the highest metal layer, and sometimes it is necessary to add jumpers to the connection.


Figure 3 jumper disconnects long runs close to the grid to reduce charge accumulation. Source: pulse

The jumper breaks the long track close to the grid, reducing the charge accumulated in the manufacturing process below the safety limit. The jumper is constructed so that the long track is connected to the gate only after it is also connected to the diffusion contact, and then allows the charge to diffuse to the substrate through diffusion. Jumpers can be used to effectively control antenna problems, but the wiring is complicated by the addition of a large number of additional vias and small wires to the layout.


The alternative solution of Fig. 4 uses a reverse connected diode close to the gate to safely dissipate the charge. Source: pulse

Another solution is to place a reverse connected diode near the gate. The diode does not reduce the antenna effect, but allows the charge to dissipate safely to the substrate during the manufacturing process. For convenience, some transistors pcell can optionally add a diode to each gate in the layout. Diodes are a very effective way to prevent antenna effect damage, but the disadvantage of inserting diodes into the circuit is that they will increase additional capacitance, which will affect the circuit performance and increase the area.

Like many aspects of analog layout, there is no “right way” to control antenna effects. The layout designer must weigh the pros and cons in each case.

After starting his EDA career as a software engineer of zuken redac in 1996, mark Waller co founded pulse in 2000 and served as vice president of R & D for more than 15 years. After the interruption of his career as a high school physics teacher, Waller now returns to pulse and leads the user support of the animate product line.

Edit: hfy


Leave a Reply

Your email address will not be published. Required fields are marked *