The loss of signal integrity in interconnection is a key problem for the highly complex SOC of several thousand megahertz, so some special methods are often used in the design and test to solve this problem. JTAG boundary scan architecture is used to test the delay violation on the interconnection of high-speed system on chip (SOC).
The loss of signal integrity in interconnection is a key problem for the highly complex SOC of several thousand megahertz, so some special methods are often used in the design and test to solve this problem. We believe that integrity loss (sometimes referred to as integrity failure) occurs when the voltage distortion (noise) and time delay damage (offset) exceed the acceptable threshold. Such a threshold depends on the process technology used in manufacturing. There are many unexpected reasons for the occurrence of this kind of fault, including: 1. Process changes of parasitic values, such as transistor size, transconductance, threshold voltage, parasitic resistance / inductance / capacitance, and transmission line effects, such as crosstalk, overshoot, reflection, electromagnetic interference, etc, These problems are difficult to analyze, and there will be varying coupling effects between interconnects (such as coupling capacitance and mutual inductance) in the manufacturing process. 2. The rebound of ground wire caused by simultaneous switching of switches in SoC usually results in the change of noise margin.
Integrity failure model
The most widely used model is the largest intruder (MA) fault model, which is a simplified model used by many researchers for crosstalk analysis and testing of long-distance interconnection. As shown in Figure 1, the model assumes that the signal transmitted on the V (victim) line will be affected by the signal / change on another adjacent a (intruder) line. This coupling effect can be generalized by the general coupling element Z. In general, the consequences of this impact are noise (causing ringing and functional errors) and time delay (causing performance degradation).
This paper uses the same model. However, we need to emphasize that there is still debate on which mode will cause the greatest integrity loss. Obviously, the traditional MA model only considers the coupling C, and all intruders make the same jump at the same time, while the victim either keeps unchanged (for the maximum ringing) or makes the opposite jump (for the maximum delay). When mutual inductance works, some researchers use other methods (pseudo-random or constant) to generate test mode to form the maximum integrity loss. Although we still use the MA model, the test method does not depend on the test pattern. In this article, assuming that the test patterns have been identified, readers can see how they are efficiently fed into the interconnect via the enhanced JTAG architecture.
Integrity loss sensor (ILS) unit
As the integrity loss in gigahertz chips has been paid more and more attention, some researchers have developed a series of on-chip sensors. Many of these integrity loss sensors (ILS) are based on amplifier circuit, which can detect voltage damage and delay threshold. BIST (built-in self-test) structure using D flip-flop is recommended to detect the propagation delay deviation of op amp. During the test mode, the op amp to be tested is either placed in the voltage follower configuration to detect the slope deviation, or placed in the comparator configuration to detect the signal propagation delay deviation.
IDDT and boundary scan method are used to solve the bus interconnection defects. In this case, a built-in sensor is integrated into the system. The sensor is an on-chip current mirror, which can convert the scattered charge into related test time. Noise detector (nd) and offset detector (SD) are both based on improved series coupled PMOS differential sensing amplifier, so they are very cheap. These units are close to the end of the interconnection and sample the actual signal and noise. Whenever the noise or offset is higher than the acceptable limit, these cells generate a 1 to 0 jump, which is stored in the trigger for further analysis.
Someone provides a more expensive but more accurate circuit, which can test jitter and offset in picosecond level. This circuit is called EDTC, which samples signals in a non intrusive way and sends test information through Low-speed serial information. When the cost is not a problem, the concept of precise signal monitoring can be accepted by researchers, and even lead to the idea of on-chip oscilloscope.
Although any ILS sensor can be used for integrity loss detection, we have developed our own ILS unit for the purpose of simplicity, economy and experiment. The circuit and function of this unit will be briefly introduced below, but the detailed function of this unit is beyond the scope of this paper.
The ILS used in this example is the time delay destruction sensor shown in Figure 2. The acceptable delay range (ADR) is defined as the period of time at which the trigger clock begins, during which all output jumps must occur. The test clock is used to create a window to determine the acceptable offset range. If the jump of input signal a occurs within the time when B is logic ‘0’, then signal a is within the acceptable delay range. Any jump occurred in the time when B is logic ‘1’ is passed to XNOR gate through transmission gate, which is realized by dynamic pre charging logic. Adjust reverser 1 according to reasonable delay range. When there is a signal jump in the time when B is 1, the output C will be 1 until B becomes 0 and the next precharge cycle begins. The output is used to trigger a trigger. Figure 3 shows the SPICE simulation of input signal a with two signal jumps, using 0.18 μ M technology. The first signal jump occurs at 0.2ns when B is 0 and the output remains 0. The second signal jump occurs at 3.5 ns, when B is 1. Because the acceptable delay period is exceeded, output C remains at 1 until B becomes 0. The time delay sensor can also detect jump errors caused by crosstalk. The pulse can be fed back to the trigger to store the delay event for further reading / analysis.
Enhanced boundary scan cell
Boundary scan is a widely used test technology, which requires the configuration of boundary scan unit between input or output pins and internal kernel logic. Boundary scan test technology can test kernel logic and interconnection efficiently. Figure 4 shows a conventional standard boundary scan cell (BSC) with shift and update nodes. Mode_ 1 put the unit in test mode. In the scanning operation, the data is shifted through the shift register (shift Dr state). The test mode which is scanned into the boundary scan unit through the scan input port (TDI) is used in parallel in the update Dr state (update Dr signal). The boundary scan unit connected between the internal logic and the output pin can capture the circuit response in parallel and scan the output through the scan output port (TDO). JTAG standard (IEEE 1149.1) can be used to test the bonding, open circuit, short circuit and other fault conditions of interconnection, which is realized by “extest” instruction. Under this instruction, TAP controller uses BSC to separate kernel logic from interconnection. But the purpose of this kind of test is not to test the signal integrity of interconnection. In order to test the signal integrity of interconnection, we need to make some improvements to the standard architecture.
Monitoring BSc (OBSC)
It is suggested to place a new BSC using ILS unit on the receiving side of the interconnection, as shown in Figure 5. This new BSC is called monitoring BSc (OBSC). ILs are added to the receiving unit, which can capture the signal with noise and delay at the end of the interconnection. If it receives a signal with integrity problems (such as time delay violation), it will output a pulse at the output and set the trigger to “1”. OBSC has two working modes
1) Integrity mode (Si = 1): select signal F. In each shift Dr state, the captured integrity data is output through the scan chain and used for the final evaluation.
2) Normal mode (Si = 0): in this mode, ILS is isolated and each OBSC is used as a standard BSC.
In the process of scanning output, we need to capture the output f signal and send it to FF1. In this case, SEL should be set to 0, so Si and shiftdr should be 1 and 0, respectively. When the scan output process starts, D1 is transferred to Q1 and used as the TDI for the next unit. After the signal integrity information is captured into FF1, the ILS trigger is reset. After the F value is sent to Q1, the scan chain must be formatted. During the shift Dr state of this example, the TDI input must be connected to FF1. Therefore, SEL must be set to 1 (Si =’1 ‘, shiftdr =’1’) to isolate the ILS path. As shown in Figure 5, Si and shiftdr need to perform or operate to select and send signal f to D1, and generate scan chain for scan output.
Figure 6 shows the dependency of sel with Si and shiftdr. As shown in the figure, in the capture Dr state, the signal f is selected, the scan chain is formatted in the shift Dr state, and the output data is scanned according to the number of lines tested. The truth table of signal sel is given in Table 1. Only one control signal (SI) is generated by the new instruction. There are three ways to monitor signal integrity information: 1) read out after applying each test mode; 2) Read out after applying test mode subset; 3) After applying the whole test mode, it can be read out at one time. Which method to choose depends on the acceptable time cost. The first method is very time-consuming, but it can display the integrity information of each interconnect in as much detail as possible. The third method is very fast, but the integrity information is relatively small, because it can only get the information of which mode or which mode subset causes the integrity failure, and can not get the failure type. Method 2 can help users strike a balance between test time and accuracy.
Figure 7 shows the overall test architecture for small SOC, in which JTAG inputs (TDI, TCK, TMS, trst and TDO) are used without any modification. But a new instruction is defined, which is mainly used to read test results in signal integrity test. As can be seen from Figure 7, only the receiver unit of each interconnection is changed to OBSC. For bidirectional interconnection, OBSC unit is used for bilateral interconnection between core J and core 1. Other units are standard BSCs, which appear in the scan chain during the signal integrity test mode. The function of ILs is independent, and no special control circuit is needed to control the timing of such units. The integrity information displayed by F is scanned and output to determine the faulty interconnection.
1. Ex-sitest directive
For the new test architecture, it is proposed to add a new instruction ex-sitest in IEEE 1149.1 instruction set. This instruction is similar to the extest instruction, but the control signal Si is added. In the update IR state, this instruction is decoded and generated (SI)_ 1)。 At this time, the output unit is used as the standard BSC, and the input unit is used as OBSC. The signal f is captured in the capture Dr state and shifted outward at the speed of each clock cycle during the shift Dr state. In this case, the TAP controller state does not change, but some changes are needed when the instruction is decoded. The data flow of ex-sitest instructions between cores is shown in Figure 8.
2. Test process
Firstly, the TAP controller IR is loaded by ex-sit instruction, and then all test modes are applied to the interconnection. At the same time, the ILS unit captures the signals at the end of the interconnection and detects all possible faults. At the end of the test application process, the results stored in ILs unit FF must be read. Monitoring process can use one of three methods. For example, use method 3, apply all test modes, and then read out the integrity information at one time.
3. Test data compression
In the traditional boundary scan architecture (BSA), the test pattern is scanned one by one and applied to the interconnection. For example, in the n-bit interconnection using the maximum intruder (MA) fault model, 12 test modes are applied to each victim line, and 12n clock is required when applying the test mode to the victim line. The total number of clocks (the number of test applications) is 12n2. Of course, Ma is a simplified model. If more complex models are used or there are a lot of interconnects in SOC, the number of test modes will increase sharply, so compression is necessary. This paper introduces a simple and effective compression technology for adding boundary scan architecture. Due to the limited space, this paper can only give a brief introduction to illustrate the flexibility of the incremental JTAG architecture.
There are two key points in this compression technique. First of all, our method is a simple lossless compression method, which constructs the compressed bit stream by determining the maximum similarity between two adjacent modes and covering them. Secondly, since this compression method is neither destructive nor reordering, no additional decompression hardware is needed. Moreover, the automatic test equipment (ATE) is only used to control the JTAG TMS to control the input to perform the decompression process. When test patterns are generated, a large number of unimportant patterns often appear in the test pattern set. The same is true for the patterns generated for signal integrity, especially when considering regional metrics (limiting development pattern space). In any case, we assume that the test set consists of the same length of patterns that contain unimportant information. Figure 9 shows our basic idea of compression, that is to make full use of the unimportant part to cover as many bits as possible to complete two modes VI and VJ (length is 1_ 16) The compression of.
Summary of this paper
In this example, the compressed data (VI, VJ) scan input only needs 21 clocks, while the uncompressed data needs 16 + 16 = 32 clocks. It should be noted that in order to decompress the specified data stream, we need a pattern and a number (such as Di and DJ in this example) to construct (decompress) the pattern. For the purpose of boundary scan testing, these numbers are the number of shifts (real-time clocks) required before updating the BSC cell content. We assume that ate stores decompressed data (d = 0 ≤ D ≤ 1). When scanning the input bit stream, the data will activate TMS (test mode selection) signal after D clocks. Then the TMS signal causes the TAP controller to generate the correct control command (such as ex-sitest) for signal integrity test. Therefore, there is no need for additional decompression hardware in our architecture.