The operation command of the data memory of the out of chip program memory of the single chip microcomputer is different from the commonly used memory, the AT24C02 of the I2C bus, and the SPI protocol. It refers to the special interface circuit and the “three bus” mode of P0 port, P2 port address bus and control line. When programming, it is different from accessing internal program memory and data memory: 1. For external program memory, the same as internal program memory, the program does not need to be changed. 2,。 For off chip data storage, assembly uses MOVX dptr or something, I don’t understand, C language related parts such as: variable keyword: pdata XDATA is the type of off chip data memory. The register address of the transferred off chip data should also be delivered according to the actual transmission, and there is no difference in other aspects. Did not say to operate special registers..

Before designing the off chip program memory, the level of EA pin must be determined first.

EA = 0, MCU only access external program memory, for 8031 MCU, this pin must be grounded. EA = 1, MCU access internal program memory, for 8xx51 MCU with internal program memory, this pin should be connected to high level, but if the address value exceeds 4KB range, the MCU will automatically access external program memory.

How to design out of chip program memory for single chip microcomputer

After setting EA, the MCU will execute automatically according to the order set by the program.

In programming, no special statement is needed to specify that the external program memory is called. For example, if EA is set to be connected to high level, the program will automatically transfer to the off chip program memory after executing the program memory instructions on chip, without special command. This is the so-called program memory is a unified address inside and outside the chip, while the data memory is treated with MOV and MOVX respectively.

But the building mainly knows the process of reading the off chip instruction code: addressing first, then fetching. According to the value of PC, MCU will first send a gate address (PC value) to P2 and P0, and then read the code from the off chip program memory. Because PC values are generally continuous, it requires that the program memory space outside the chip should be continuously distributed, which is different from data memory. If the distribution is discontinuous, it is necessary to change the value of PC with special line number to make it correspond to the distribution of off chip program memoryIn short, remember the way of three bus transmission, addressing first, then data transmission, controlled by the control busMemory generally has WR, RD, Cs lines and address port, data port, some data address port multiplexing, some separate. Look at the datasheets of these memories to see how to access their internal data. For example, read out the data in the external RAM address of 0x0001 (assuming there is this address), then set WR to high, CS to low, and output 0x0001 on the address line. Then the CPU data line can wait for the required data. In this case, the CPU I / O is just a common I / O port. However, the general microcontroller and arm can choose I / O as the access port of external memory. At this time, as long as the corresponding line is connected according to the instructions in the datasheet, the CPU can automatically cooperate in the timing according to your instructions, so that accessing external devices is just like accessing internal RAM. The advantage of this is to save CPU time.

The C language instruction of setting address 0x0001 to 0x55 is

(* (unsigned char *) 0x0001) = 0x55; / / where the data width is 8 bit

If the function of I / O port selection is external data address bus, and the hardware is connected well, then this instruction is to read and write the corresponding address of external memory.

It is worth mentioning that the access speed of various types of memory devices is different. Therefore, if the program is executed in external devices, the execution time will be quite different. For example, the execution speed of a for loop in external RAM and external flash may be three times lower.

First, single chip microcomputer adopts three bus structure to transmit data. Address bus, data bus and control bus. The process of transferring data is addressing first and then transferring data. That is to send an address information (the MCU writes address information to the bus), and the register (program memory or data memory) writes the data to be read by the microprocessor to the bus according to the address, and then the microprocessor reads the data. The whole process is controlled by control bus. Therefore, the data read each time is aimed at the register corresponding to that address, and there will be no confusion. When writing data, address first, then write data, and the data will be written into the register corresponding to the address just addressed.

Second, program memory and data memory have different strobe signals. In an instruction cycle, they are gated at different times, so there will be no confusion.

Third, gate pin is different. Take the off chip data memory for example. Pins 6 and 7 of P3 are used as gating signals, and PSEN is used for program memory. They are connected to the gate pins of their respective devices, so there is no confusion.

Fourth, the instructions are different. Take assembly instructions. Mov is used to transfer data from program memory, and MOVX is used to transfer data from data memory (for off chip).

In a word, remember the three bus transmission mode, addressing first, then data transmission, controlled by the control bus, this mode, you can easily understand this.

The P2 and P0 of the single-chip microcomputer transmit the high eight bits and the low eight bits of the address respectively. At the same time, P0 also transmits data. During ale high level of timing signal, address information is locked. /PSEN is strobe memory. Program code is transferred to program memory during / PSEN low level, and / WR and / RD are gated data memory, that is, data is transferred to data register during / WR and / RD low level. While / PSEN and / WR and / RD become low levels at different times, and there is no overlap. That is to say, when / WR and / RD become low level, / PSEN has recovered to high level. Of course, the data information from port P0 will only be transferred to data memory, because the program memory is no longer in the strobe state! From the surface, it is from the port P0, but because of the time of gating device is different, there will be no confusion. Of course, what I’m talking about is the off chip program memory and data memory. In fact, the same is true for the on-chip program memory. The three bus control mode enables them to be gated at different times without conflict.

Take a look at a single-chip circuit diagram. You will find that P0 is connected to both 74ls373 and 8155 or 8255 or keyboard or DAC. And 8155 or 8255 or keyboard or DAC are treated as data memory for MCU. Most of the 74ls373 is program memory. So the signal sent by P0 is not both accepted? Pay attention to the G interface of ale to 74ls373, latch address is used, PSEN is sometimes used, sometimes not. WR and RD are connected to strobe interface of data memory. Since the signals of WR, RD and ale do not overlap in time, the signal of P0 will not be received by program memory and data memory at the same time. This is an example, and the specific situation should be analyzed in detail.

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