Sampling signal by ADC is a common task of MCU application, which can convert continuous analog signal into a series of discrete digital data for MCU processing. In some applications, a single ADC needs to sample multiple channels at a high sampling rate. For example, the management subsystem of power monitoring system needs to sample the output of multiple regulated power supplies to monitor the working state of the system; another example is that in sensor based applications, MCU needs to sample multiple sensors to achieve system feedback.

One of our customers wants to use a piece of cypress psoc4 to realize the design of sampling 16 channels with 1msps sampling rate. The total sampling time of 16 channels can not exceed 19 μ s. But the built-in multiplexer (sarmux) of psoc4 only supports 8 channels. This paper will introduce how to overcome this design problem through the internal programmable module of PSoC.

Analyze design requirements

First of all, we need to carefully analyze the design requirements. The customer regards the complete sampling of 16 inputs as one sampling period. As shown in Figure 1, the maximum length of a sampling period is limited to 19 μ s. Interrupt service request (ISR) can be used to store the sampling results between each sampling period.

How to design 16 sampling channels by PSoC internal programmable module

Figure 1: timing of 16 channel sampling.

In order to achieve this goal with an 8-channel SAR, we need to use the universal programmable digital module (UDB) in psoc4 to realize the customized design. The design uses the digital signal interconnection (DSI) in psoc4 chip to realize the multiplexer switching sampling channels, and buffers the sampling results in the FIFO based on datapath at the end of the sampling period, and then reads them out through the interrupt service subroutine (ISR).

Data path is the most flexible part of UDB module. Each UDB module contains a data path, and each data path contains an 8-bit Alu with multiple registers. For a detailed introduction of UDB structure and data path function, please refer to psoc4 technical reference manual. Each data path can implement an 8-byte FIFO. We need four FIFOs to buffer 16 12 bit SAR samples.

Figure 2: 16 channel SAR sampling.

Figure 2 shows a DSI based multiplexer that automatically switches the current sampling channel between multiple inputs. Figure 3 shows an overview of the hardware FIFO.

Figure 3: four 8-byte FIFOs for buffering sampling results.

Configure SAR components

The SAR is configured as a single input channel in single ended mode, with input voltage ranging from 0 to VDD and 1msps sampling rate. After receiving the sampling trigger signal, SAR starts to collect the input signal. After the acquisition, a “sdone” signal is generated, which is sent to DSI network and named “ADC”_ SDONE”。 The SAR component provided in the standard component library of PSoC creator cannot support the output of sampling results to DSI bus. Therefore, we need to import the SAR component into the project and modify it, as shown in the red part of Figure 4.

Figure 4: detailed design – modifying SAR components.

Figure 5 shows the output connection of the SAR component. In SAR_ After the start function, we need to add a line of code to enable SAR to output the sampling results to DSI network, as follows:

// start SAR component and wait for conversion trigger

SAR_ Start();?

// enable SAR sampling result output on DSI

*((reg32 *)(SAR_ SAR_ CHAN_ CONFIG_ IND + (uint32)(0 《《 2))) |=


Figure 5: detailed design – output connection of SAR.

Multiplexer based on DSI

As shown in the blue part of Figure 6, sarmux is replaced by hardware multiplexer controlled by DSI to switch 16 channels. Using switch_ CLK clock triggers count7 unit to generate channel selection signal, so each channel conversion can be divided into two stages: signal acquisition and conversion.

Figure 6: MUX and trigger signal generation based on DSI.

After the signal acquisition, the signal will remain in SAR, and the input channel can be switched at this time. Therefore, the sdone used to display the completion of signal acquisition phase can be used for channel switching. In fact, switch_ CLK is based on DSI signal “ADC”_ The clock defined by sdone (sdone) is shown in the “cydwr” page of Figure 6.

Figure 7: clock definition for design scope resources.

Count7 unit is a custom component, not in the scope of standard component library. It is a decrement counter that outputs the current counter value to DSI. The default initial value is 0x7F. Therefore, the channel selection range is from # 15 to # 0. Add the following code in the main program to control count7.

/* Enter critical secTIon */

interruptState = CyEnterCriTIcalSecTIon();

/* Set the Count Start bit */

MYCOUNT7_ AUX_ CTL |= (1 《《 5);

/* Exit criTIcal section */


// set default value of count7 as 0x7F


Sampling trigger for SAR generation

Step 1: generate the next trigger signal before completing the current sampling

Since there is only one actual input for SAR, once the current channel is sampled, SAR needs to trigger signal for next sampling. Many signals are suitable for this purpose, but the selection of trigger signal should follow the following two rules:

1. There should be no interval between the trigger signal and the completion of the current sampling, even the trigger signal can occur in advance, so as to reduce the delay.

2. The trigger signal must ensure that the current sampling work will not be damaged.

According to the above rules, sdone and EOC can be selected for triggering. However, using EOC will make the sampling time of each channel to ~ 1.4 μ s, which is due to the overhead between the rising edge of trigger signal and the beginning of SAR sampling. SAR requires at least 5 saradcs_ CLK clock to convert DSI trigger signal to signal sampling start. Our design is more demanding. EOC signal and saradc_ The rising edge of CLK is synchronous. After passing through the DSI network and arriving at the SOC of SAR, it has lagged slightly behind the rising edge of the sampling clock. Therefore, it requires six saradcs_ CLK clock or about 340ns trigger time consuming.

We have to look for another trigger. Fortunately, when SAR is working, it can store one trigger signal, but only one, for the next scan. So we can use sdone to trigger the conversion. By paralleling the trigger generation time with the SAR conversion time, SAR can store the trigger event before the current conversion is completed. Now for 16 channel sampling, we can have a conversion time of 1 μ s (see sdone cycle in Figure 12).

Step 2: stop the trigger signal generation temporarily at the end of each sampling period

At the end of each sampling period, we need to stop the trigger signal generation temporarily, otherwise the continuous sampling will overflow the FIFO. As shown in the red part of Figure 6, when channel 0 is selected, the synchronous D flip-flop (DFF) needs to be turned off to temporarily stop the flip-flop output. After the FIFO is cleared by ISR, the count7 unit needs to be reset by using 0x7F to re enable the DFF output. At the same time, the firmware trigger mode should be used to start the sampling of the first channel in the new cycle, as shown in Figure 8.

Figure 8: SAR ADC timing.

FIFO control

UDB can be configured as 8-byte FIFO to store data from DSI network. Figure 9 shows an overview of configuring data paths. FIFO clock samples data to FIFO. F0 load and F1 load are responsible for enabling or disabling FIFO. Two status signals can prompt FIFO full event.

Figure 9: data path configuration for 8-byte FIFO.

Fig. 10 shows the working sequence of FIFO. The 12 bit SAR results are stored in LSB_ FIFO and MSB_ FIFO. The count7 unit sorts channels from 15 to 0. Therefore, channels 15 to 8 are stored in the upper FIFO and channels 7 to 0 are stored in the lower FIFO. The load signal is generated according to the full status and the enable signal.

Figure 10: FIFO timing.

Once the results of the last four channels are stored, ISR will be triggered to read FIFO. FIFO enable uses the bit of count7 cell (as shown in the red part of Figure 11), which is also associated with switch_ CLK (sdone) synchronization. This ensures that changes in en do not disrupt FIFO sampling.

Figure 11: detailed design of generating en for FIFO.

Design test

Figure 12 shows a sampling period. Sixteen sdone and EOC pulses represent channel conversion. Sixteen fifoclks and one FIFO full signal can buffer the last four results to explain the FIFO working state. Note that the interval between sdone and fifoclk is 1 μ s.

Figure 12: test results – signals in one sampling period.

Fig. 13 is a waveform of multiple sampling periods. The interval between two cycles of storing data from FIFO to SRAM is about 9.56 μ s.

Figure 13: test results multiple sampling cycles.

Editor in charge: GT

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