With today’s advances in wireless technology, more attention is being paid to component performance. This article will discuss ceramic and ceramic chip capacitors and understand their behavior in RF product designs. They are an excellent choice for wireless applications where volume efficiency, reliability, and RF performance are absolutely required.

design standards

The most commonly used design categories for ATC ceramic chip capacitors are multilayer (MLC) and single layer (SLC). MLC uses multiple or stacked electrode sections while SLC contains two electrodes separated by a dielectric. Both are constructed according to the following design criteria:

  • Ceramic and Porcelain Dielectrics
  • Strong sealed structure
  • Optimized Electrode Pattern
  • Low resistance electrode and termination materials
  • high dielectric strength
  • Protective barrier layer (MLC) between electrodes and terminals
  • Direct surface mount on microstrip
  • Ultra stable in temperature and humidity
  • Q very high
  • low dissipative loss

Choose the right capacitor

When selecting ceramic chip capacitors for RF wireless applications, it is important to establish overall circuit performance criteria. Components should then be matched to specific application requirements. A shopping list of typical performance requirements for this circuit component might include the following:

  • Capacitance (pF)
  • tolerant(%)
  • Rated voltage (WVDC, VRMS)
  • Equivalent Series Resistance (ESR)
  • Temperature Coefficient (TC, PPM/°C)
  • Dissipation coefficient (%)
  • Series resonant frequency (Fsr)
  • Parallel resonance frequency (Fpr)
  • Insulation resistance (IR)
  • Dielectric aging effect (% of hours per decade)

Performance

An ideal capacitor stores all of its energy in the dielectric, which is 1/2CV². However, realizable capacitors will always exhibit some series resistance, which must be accounted for. The series resistance known as Equivalent Series Resistance (ESR) is always one of the most important factors to consider in RF circuit design. It is mainly attributed to the effect of dielectric loss and metal loss of electrodes and termination materials. Also, proper control of the manufacturing process must be in place at each stage to ensure optimum ESR performance. In the low frequency region from Hz to KHz, the main contribution to ESR is dielectric loss. However, at RF frequencies, ESR is mainly due to metal losses (i.e. electrodes and terminals).

Most manufacturers usually express ESR in milliohms at a specific frequency. The standards most often used as guidelines are EIA RS483 and MIL-C-55681. Measurements are performed at various frequencies between 30 MHz and 1 GHz. Therefore, it is necessary to consider the ESR value at your specific design frequency. For example, if you are designing for a wireless application at 900 MHz, and the ESR is specified as 150 MHz, you can calculate the ESR for 900 MHz by multiplying the specified ESR for 150 MHz by √900/150. This relationship holds up well for RF and accounts for the “skin effect”. ESR is the main loss element of a capacitor and is used to determine power loss, ie: P = I²*ESR.

Quality factor (Q) is the figure of merit and is a measure of a capacitor’s ability to store energy in a dielectric. Since Q = Xc/ESR, it is clear that low ESR produces high Q. As with ESR, Q must be specified or calculated at the design frequency.

Dissipation factor (DF), also known as loss tangent, is the reciprocal of Q, ie DF = 1/Q. With an ideal capacitor, the current can lead the voltage by 90 degrees. However, a real capacitor will have a small angle called the dissipation angle. The tangent to the loss angle is equal to the dissipation factor, which indicates what portion of the total reactive power in the capacitor will be lost as heat, i.e., dissipation loss.

Example: loss angle = 3 degrees;
So DF = tan3 = 0.05 or 5%.

In the example above, the dissipation factor is 0.05 or 5%. This means that 5% of the total power in the capacitor is lost due to heat. Please refer to Figure 1.

Selecting RF Chip Capacitors for Wireless Applications

Another major concern in wireless design applications of parasitic behavior is the electricalanti-Component parasitic behavior. Capacitors can be modeled with equivalent circuit elements that take into account parasitic effects. Figure 2 shows the lumped element model and is valid for chip capacitors in these applications. Using the model can help designers determine properties such as series resonant frequency (Fsr), equivalent series inductance (ESL) and transfer function characteristics.

Selecting RF Chip Capacitors for Wireless Applications

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