Embedded FPGA (efga) refers to embedding one or more FPGAs into ASIC, ASSP or SOC chips in the form of IP. In other words, efga is a digital reconfigurable structure, which is composed of programmable logic in programmable interconnection. It is usually represented as a rectangular array, and the data input and output are located around the edge. Efgas usually have hundreds or thousands of inputs and outputs and can be connected to bus, data path, control path, GPIO, PHY or any required device.
All efgas use lookup tables (LUTS) as their basic building blocks. LUT has n inputs, select a small table, and its output represents any required Boolean function of N inputs. Some efgas LUTS have four inputs and some have six. Some LUTS have two outputs. LUT usually has a trigger at the output; These can be used to store results. These LUT register combinations usually appear in Quaternary form, as well as carry arithmetic and shifters to effectively implement adders.
The LUT receives all inputs from the programmable interconnection network and feeds back all its outputs to the programmable interconnection network. In addition to LUT, efgas may also contain MAC (multiplier / accumulator module). They are also connected to programmable interconnection networks to provide more efficient digital signal processing (DSP) and artificial intelligence (AI) functions. For memory, there is a lot of ram, usually in a dual port package. As for LUT and MAC, it is connected to the programmable interconnection network through ram.
The efgas has outer loops of input and output pins that connect the efgas to other parts of the SOC, and these pins are also connected to the programmable interconnection network. Software tools are used to synthesize Verilog or VHDL code to program efgas logic and interconnection to achieve any required functions. Efga is a convenient new logic block, which can improve the value of SOC in many aspects, including: extensive and fast control logic using hundreds of LUTS; Reconfigurable network protocol; Reconfigurable algorithms for vision or artificial intelligence; Reconfigurable DSP for aerospace applications; Reconfigurable accelerator for MCU and SOC.
Today, there are already some efgas suppliers, mainly including achronix, flex Logix, menta and QuickLogic. In addition, there are some smaller suppliers. With these choices, customers need to decide which one best meets their needs. So, how to choose? Although commercial factors need to be considered, this paper focuses on technical factors.
Step 1: process compatibility. Generally, even in the early stage of IP evaluation, the company will choose foundry plant and process node. TSMC, Globalfoundries and SMIC are now or are developing efgas for 65nm, 40nm, 28nm, 22nm, 16nm, 14nm and 7Nm process nodes. However, not all suppliers have efgas for all OEM / process nodes, at least not yet. It is important to check what is compatible with your process through their website. You should also see whether the efgas discussed has been verified in the chip and provide a report under NDA.
Don’t forget to check the compatibility of the metal stack. The key IP you choose, such as SerDes or your application, may require you to use a specific metal stack, but not all efgas IPS are compatible with all metal stacks.
Step 2: array size and function. Not all efgas suppliers can make very small-scale efgas. At the same time, not all manufacturers can make very large-scale efgas. In addition, the nature of MAC and ram they support may be different. For whether you need hundreds of LUTS or hundreds of thousands of LUTS, and your requirements for Mac and ram, this may screen out some suppliers.
Step 3: use RTL for benchmarking. The efga supplier will provide you with software for evaluation so that you can determine (RTL) the silicon area and performance that each efga can achieve. You need the efga to operate in the same temperature and voltage range as the rest of the SOC, so make sure you need support.
When benchmarking, it is important to compare apples to apples. For example, you should compare each efgas at the same process (slow / slow or typ / typ or fast / fast) and at the same voltage and temperature. You should expect that software tools from efga vendors will allow you to check performance under different process corners and voltage combinations.
Note that your RTL is suitable for efgas. If RTL is used in hardwired ASIC design, there are often 20 ~ 30 logic layers between triggers. If you put it in an eofpga without optimization, it will run very slowly. In efgas, LUT output always has triggers. You can use them to add more pipelines to RTL to obtain higher performance in efgas.
A 16 bit adder. What you care about is how fast it runs, but if you are not careful, the results may surprise you. Now imagine a large efga. If the adder is placed in a corner of the array and the input and output are close, the performance will be much higher than that of finding the adder in the middle of the array. This is because if you observe the performance from array input to array output, when the adder is in the middle of the array, the distance to the adder of data input and adder output will be longer. In fact, the adder is the same and runs fast in both positions. The problem is that your test does not isolate the performance of the adder, but it also adds the signal required to reach the adder.
In order to cope with this effect, especially because you may compare two different sizes of efgas, what you need to do is set registers on the input and output, which can ensure that the performance you care about can be measured, regardless of the size and location of the array.