In the more complex board design, you have to make some design tradeoffs. Because of these trade-offs, there are some factors that will affect the design of PCB power distribution network.

How to balance the power design of PCB

When the capacitor is installed on the PCB, there will be an additional loop inductance, which is related to the installation of the capacitor. The value of loop inductance depends on the design. The size of the loop inductance depends on the line width and length of the line from the capacitor to the via, the length of the line, that is, the length of the connecting capacitor and the power / ground plane, the distance between the two holes, the diameter of the hole, the pad of the capacitor, and so on. As shown in Figure 1, the installation figures of various capacitors are shown.

How to balance the power design of PCB

Figure 1 best and worst capacitor layout

The design points of reducing the inductance of capacitor circuit are as follows

The hole should be placed as close as possible to the capacitance. Reduce the hole spacing of power / ground. If possible, use multiple pairs of power / ground holes in parallel. For example, the two holes with opposite current polarity should be placed as close as possible, and the holes with the same current polarity should be placed as far as possible.

Connect the hole and capacitor pin with short and wide wiring.

■ place capacitors on the surface of PCB (top and bottom) as close as possible to their corresponding power / ground plane. This reduces the distance between the holes. Use a thin electrolyte between power and ground.

Then there are three different cases of design, for the capacitor installation and propagation inductance. Figure 2 shows the introduction of loop inductance in various design situations.

How to balance the power design of PCB

Figure 2 design

Case 1-poor design

■ designers do not pay attention to the design of power distribution network (PDN).

The spacing of holes is not optimized.

■ the distance between power supply and ground plane is not optimized.

The routing distance between the hole and the capacitor pin is long.

As for the inductance of the whole circuit, the inductance of the circuit mainly comes from the wires, because compared with the other two cases, the length of the wires in the poor design is five times that of them (good design and very good design). The distance from the bottom layer of the installed capacitor to the nearest plane is also the main factor of the loop inductance. Because there is no optimization (10mil), the influence of wiring on the inductance of the whole circuit is very large. Similarly, because the designer uses 10 mil of dielectric material between the power supply and ground, the secondary factor of loop inductance comes from the propagation inductance. If the distance between vias is not optimized, it is less significant than the length of the vias. The influence of the hole becomes greater with longer vias.

Situation 2 – good design

The designers pay attention to the design of partial power distribution network (PDN).

The spacing of holes is improved. The length of the hole remains unchanged.

■ the distance between power supply and ground level has been improved.

The routing distance from via to capacitor pin is optimized.

The loop inductance of the wiring is still the main contributor of the whole loop inductance. However, the inductance of good design is about 2.7 times smaller than that of poor design. Because the designer reduced the thickness of the dielectric from 10 mil to 5 mil, the propagation inductance was reduced by half. Because the distance between vias is reduced, the influence of vias is improved a little.

Situation 3 – very good design

Designers pay great attention to the design of PDN.

The spacing and length of holes are improved.

The distance between power supply and ground is also fully optimized.

The routing distance from via to capacitor pin is optimized.

The inductance of a very good design is about 7.65 times smaller than that of a poor design. Due to the reduction of the wiring length, the thickness from the bottom surface of the capacitor installation to the nearest plane layer on the PCB board is reduced, which achieves the purpose. Because the designer has optimized the thickness of electrolyte layer between power supply and ground, the propagation inductance will be greatly reduced. Due to the reduction of the hole spacing and hole length, the loop inductance of the via is also improved significantly. Compared with the poor design, due to the reduction of one of the seven main factors, the total loop inductance of the very good design is reduced..

On PCB board, additional inductance of via circuit is introduced by installing capacitor, which reduces the resonant frequency of capacitor. When you design a power distribution network (PDN), you must consider this factor. In high frequency design, reducing the loop inductance is the only visible way to reduce the impedance.

For a given power supply, the report generated by PDN tool shows that the cutoff frequency of PCB with very good design is higher than that with poor design. This may be the opposite of the expected result, because decoupling at a higher cut-off frequency requires more capacitance than decoupling at a lower cut-off frequency.

For a very good design, a higher cut-off frequency means that the higher frequency can be decoupled. The capacitors placed on the PCB board can decouple the noise to a higher frequency.

In the case of poor design, the PCB beyond the lower cut-off frequency cannot be decoupled. Any additional capacitance increase, that is, the decoupling capacitance beyond the cut-off frequency, can only increase the BOM cost without any influence on the decoupling effect. Compared with the very good design, for the poor design, the design of power distribution network is more vulnerable to the noise of a specific frequency

As another example, suppose a 20 layer PCB has a total thickness of 115 mil. The power layer is on the third layer. The thickness from the first layer (FPGA layer) to the third layer is 12mil. So the thickness from the bottom layer to the third layer is 103 mil. The source and the formation are separated by a 3 mil dielectric. For this kind of trace, the inductance of BGA hole is 5NH (for this kind of power trace, 5 pairs of holes). In order to cope with the tight layout and wiring area of the first layer, the decoupling capacitors associated with it are installed on the bottom layer. Due to the long vias, this tradeoff design results in a high capacitance installation inductance. After full optimization, the installation inductance of 0402 capacitor in the bottom layer is 2.3nh, while the installation inductance of the same capacitor in the first layer is 0.57nh.

In order to improve the PDN effect of the given trajectory, you can put some high-frequency capacitors in the first layer, and put the intermediate frequency and bulk capacitors in the original position, that is, the bottom layer. This circuit design is a cut-off solution for PDN, because the high-frequency capacitor is used as the first response capacitor below the cut-off frequency. The effect of capacitance depends on the total loop inductance (installation inductance + propagation inductance + BGA hole inductance) and FPGA. You can put the high frequency capacitor on the first layer and a little bit away from the FPGA. The propagation inductance of the capacitor outside the breakout region of FPGA is 0.2nh. Compared with the original method, this new method is beneficial because of the total loop inductance

The total inductance (0.57nh + 0.2nh + 0.05nh = 0.82nh) is smaller than that of the bottom layer.

The propagation inductance of PCB is related to the design. It exists uniformly in the medium between the power supply and the ground plane. The thickness of 3mil or thinner is the best design to reduce the planar propagation inductance. You can improve the performance of PDN according to the following design guidelines.

Here’s the design guidance on sequential importance, from the first level to the bottom – the design guidance on the first level is the most important.

Reduce the thickness of power supply and dielectric between layers. When designing the stack of boards, determine the power supply, layer and other layers. For example, the stack pwr1-gnd1-sig1-sig2-gnd2-pwr2 is better than the stack pwr1-sig1-gnd1-sig2-gnd2-pwr2.

The result of the second case is that there is no optimized design for the distance between the power supply and the ground. Such a setting will cause the large capacitance propagation inductance between pwr1 / GND1 to be larger than that between pwr2 / gnd2. You can find a typical 3 mil dielectric thickness between the power and ground plane at no extra cost. For additional performance improvement, consider a thinner dielectric thickness than 3 mil. However, this will cause the cost of PCB to rise.

When selecting capacitance, select multiple capacitance values instead of a large capacitance with the same value to achieve the target impedance. In PDN, the peak impedance is formed by resonant reaction. High ESR can suppress the resonance at the resonance frequency point, thus reducing the height of impedance peak. At the resonant frequency and impedance peak of the capacitor, some capacitors with the same capacitance value can cut off the ESR. A relatively high ESR can be maintained by selecting a variety of capacitors in a wide frequency range.

The position of high frequency capacitor is selected to reduce the inductance of the whole circuit. The whole inductor is composed of ESL of capacitor, mounting inductor, propagating inductor and through hole inductor of BGA. When placing capacitors, high frequency capacitors are preferred, followed by medium frequency and low frequency capacitors.

■ when dividing a plane, make sure that the plane is properly square in shape. Avoid the long and narrow plane shape, because it will limit the current and increase the propagation inductance of the plane.

The capacitors of medium frequency and low frequency are not so sensitive to how to place them. You can put them a little bit further away from the FPGA.

Trade off of multi-channel design

On a PCB with multiple peripherals, your design can no longer share a single power supply. This may require you to implement DDR power interface through your design, combine various I / O port power trajectories, or combine various receiver power trajectories to reduce PCB BOM cost and PCB layout complexity.

Power path sharing increases the complexity of PDN, and increases a lot of noise on PCB and die. For the case of multi-channel, there are two main steps to design the power distribution solution

1 low frequency solution

2 high frequency solutions

At very low frequencies, the first step is to ensure that the size of the VRM is suitable for handling various current needs.

Low frequency decoupling must consider the power supply current of various combination power supply. The bulk capacitor must be selected to cover the frequency band covered by the target impedance. It is difficult to know the frequency range precisely because there is an area beyond the impedance curve, which is based on the maximum current consumption of the given power supply area on die, rather than the current consumption of the same power supply combination associated with other currents. For the design, the frequency range of bulk capacitor decoupling is estimated from DC to about 5 ~ 10MHz.

When sharing multiple power sources, use the PDN tool in a similar way, but it is recommended that you decouple at the highest cut-off frequency. For the decoupling of single power supply and shared multi-channel power supply, this is the successful process of single PDN method design. This method is suitable for the design of power circuit with similar current requirements. However, there are several exceptions to this approach.

This example is power sharing between core power supply (VCC) and PCI Express hard IP block (vcchip). The reasons for the exception are:

The current of VCC will be much larger than that of vcchip.

Compared with VCC and vcchip, the via inductance of BGA of VCC is much lower than vcchip.

Compared with VCC and vcchip, the cut-off frequency of VCC is much lower than vcchip.

Therefore, for the power supply design, it is not suitable to use the highest cut-off frequency decoupling at the BGA via. As shown in Figure 3, the combination impedance curve of VCC and vcchip power circuit does not conform to the target impedance, which is equivalent to the cut-off frequency decoupling of vcchip. This is because the decoupling capacitance effect is limited

How to balance the power design of PCB

Figure 3 cut off frequency impedance curve of vcchip

According to the previous explanation, the high-frequency noise in the power supply trajectory is mainly caused by its own transient current. The decoupling design instruction for the highest cut-off frequency of shared circuit is based on the impedance calculation of the whole transient current, which is the requirement of “over design”.

How to balance the power design of PCB

Figure 4 sharing of changing power circuit

In this case, you must use the whole transient current to calculate the target impedance curve based on the PCB decoupling project, which is equivalent to the maximum current consumption of the cut-off frequency of the power circuit. In the example of VCC and vcchip power circuit sharing, you must use the cut-off frequency of VCC power circuit. As shown in Figure 3-A, the impedance curve of the combined power circuit with the cut-off frequency of the core power decoupling is shown. For the core power supply, the total current along the ball or via of BGA (VCC + vcchip) is used to get the impedance curve. Then you can check whether the results meet the target impedance of the individual power supply design guidelines.

Based on the same decoupling items, as shown in Figure 4-A, the impedance curve of vcchip power supply is shown in figure 4-b. However, when we get this curve, we only need to consider the current consumption and the number of BGA vias for vcchip. As shown in figure 4-b, the impedance curve of vcchip reaches the target impedance until the cut-off frequency of vcchip power supply.

The final decoupling project must reach the frequency of their target impedance. If there are some special cases that violate the design objectives, we can make small adjustments to optimize the decoupling project.

In a similar situation, any combination of power supply can be optimized according to the examples of VCC and vcchip.

On a PCB board, when multiple FPGAs need to be powered from the same power supply, you can use similar methods to deal with this situation. For the design of low-frequency solutions, we must use the total current consumption of the chip. For the design of high-frequency solutions, we must use the current consumption of one of the chips. You can use the same number of capacitors to decouple other chips at high frequencies.

Compared with the solution obtained by the field analysis tool, if the space between two FPGA chips is small, the high frequency side may lead to slight over design, because the field analysis tool considers the layout of the board. This may be because the chips are close to each other, and almost no capacitance can cut off to meet the position requirements of the two chips. It also depends on the cut-off loop inductance of the capacitor seen from the FPGA chip side.

A common design trade-off is to create a separate power plane, and power different power networks from one power supply, using filters to supply clean power to the power network. In most cases, the filter is a magnetic bead connected between two power supplies on the board. As a rule, you can follow the design guidelines below to provide clean power to a power network.

When the beads are connected to two power supply networks, make sure that the installed inductance is minimum.

■ select the beads according to the characteristics listed below to ensure that the current consumption of the power circuit is less than the rated current of the beads.

Package size (06030402, etc.)

Rated current

■ DC resistance

■ impedance at target frequency (10 MHz, 100 MHz, 1 GHz, etc.)

The frequency response of the equivalent RLC model of the magnetic bead must be consistent with that given in the datasheet.

When doing AC analysis, the model of magnetic beads and various capacitors selected to achieve the target impedance must be included in the frequency covered. When designing the equivalent RLC model of the capacitor, the installation inductance should be considered as an integral part of the model. If the peak value of AC analysis does not appear in the band of interest (DC to 200 MHz), you can use magnetic bead isolation to provide clean power.

The results of PDN obtained by the above simulation can meet the requirements of target impedance in the frequency band we are interested in.

Source: Hardware 100000 why

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