1、 Data input stage
1. Whether the data received in the process is complete (including schematic diagram, *. BRD document, bill of materials, PCB design description, PCB design or change requirements, standardization requirements description, process design description document)
2. Confirm that PCB template is up-to-date
3. Confirm the position of the positioner of the template is correct
4. Is the PCB design description, PCB design or change requirements, and standardization requirements clear
5. Confirm that the prohibited placement devices and wiring areas on the outline drawing have been reflected on the PCB template
7. After confirming that the PCB template is correct, it is better to lock the structure file to avoid misoperation and being moved
2、 Post layout inspection phase
a. Device inspection
8. Confirm whether the package of all devices is consistent with the Unified Library of the company and whether the package library has been updated (check the operation result with ViewLOG). If not, be sure to update symbols
9. Confirm that the signal corresponds to the position, the connector direction and the silk screen mark are correct, and the daughterboard has anti misinsertion measures, and the components on the daughterboard and the mother board shall not interfere
10. Whether the components are placed 100%
12. Is mark point sufficient and necessary
13. The heavier components should be placed near the PCB support point or edge to reduce the warpage of PCB
14. It is better to lock the devices related to the structure after layout to prevent misoperation of the moving position
15. Within 5mm around the crimping socket, no element with height higher than that of the crimping socket is allowed on the front, and no element or solder joint is allowed on the back
16. Confirm whether the device layout meets the technological requirements (focus on BGA, PLCC, patch socket)
17. For components of metal shell, special attention shall be paid not to collide with other components, and enough space shall be reserved
18. The interface related devices shall be placed as close as possible to the interface, and the backplane bus driver shall be placed as close as possible to the backplane connector
19. Whether chip device on wave soldering surface has been converted into wave soldering package,
20. Whether there are more than 50 manual solder joints
21. Horizontal installation should be considered when inserting higher components axially on PCB. Make room for sleeping. And consider the fixed way, such as the fixed pad of crystal oscillator
b. Function check
24. The A / D converter is placed across the A / D partition.
25. Is the clock device layout reasonable
26. Whether the layout of high-speed signal devices is reasonable
27. Whether the termination device has been properly placed (source matching series resistance shall be placed at the driving end of the signal; intermediate matching series resistance shall be placed at the middle position; terminal matching series resistance shall be placed at the receiving end of the signal)
28. Whether the quantity and position of decoupling capacitance of IC devices are reasonable
29. The signal line takes the plane of different levels as the reference plane. When crossing the plane division area, whether the connection capacitance between the reference planes is close to the line area of the signal.
32. Confirm that the circuit of strong signal and weak signal (power difference of 30dB) is set separately
33. Whether devices that may affect EMC experiments are placed in accordance with design guidelines or reference to successful experience. For example, the reset circuit of the panel should be slightly close to the reset button
34. Heat sensitive components (including liquid dielectric capacitance and crystal oscillator) shall be far away from high-power components, radiators and other heat sources
D. power supply
36. Is the IC power supply too far away from the IC
39. Is the overall layout of power supply reasonable
e. Rule settings
40. Whether all simulation constraints have been correctly added to constraint manager
42. Is the spacing setting of test via and test pin sufficient
44. Have all differential line impedances with characteristic impedance requirements been calculated and controlled by rules
3、 Post wiring inspection phase
F. digital mode
46. If the A / D, D / A and similar circuits are separated from the ground, does the signal line between the circuits go from the bridge point between the two places (except the differential line)?
48. If the formation design is adopted in an undivided way, it is necessary to ensure that the digital signal and analog signal are wired in different areas.
g. Clock and high speed part
49. Whether the impedance layers of high-speed signal line are consistent
50. Are high-speed differential signal lines and similar signal lines equally long, symmetrical and parallel to each other?
51. Make sure the clock line is on the inner layer as much as possible
52. Confirm whether clock line, high-speed line, reset line and other strong radiation or sensitive lines have been wired according to 3W principle as much as possible
53. Are there no test points on clock, interrupt, reset signal, 100M / Gigabit Ethernet and high-speed signal?
54. Is 10h (H is the height of the signal line from the reference plane) satisfied between LVDS and TTL / CMOS signals?
55. Does the clock line and high-speed signal line avoid passing through the dense through-hole area or between device pins?
56. Whether the clock line has met the requirements of (Si constraint) (whether the clock signal routing has achieved less through holes, short routing and continuous reference plane, and the main reference plane is GND as far as possible; If the GND main reference plane layer is changed during layer change, it is GND through hole within 200mil away from the through hole.) if the main reference plane of different levels is changed during layer change, is there decoupling capacitance within 200mil away from the through hole?
h. EMC and reliability
58. For crystal oscillator, is there a layer of ground under it? Does the signal wire pass through the device pins? For high-speed sensitive devices, is it possible to avoid the signal line passing through the device pins?
59. There shall be no sharp angle and right angle on the signal line of single board (generally, turn continuously at an angle of 135 degrees, and the RF signal line is best made of arc-shaped or angle cut copper foil after calculation)
60. For the double-sided board, check whether the high-speed signal line is wired close to the return ground wire; for the multi-layer board, check whether the high-speed signal line is routed close to the ground plane as much as possible
61. For two adjacent layers of signal routing, try to route vertically
62. Avoid signal line crossing under power module, common mode inductance, transformer and filter
63. Try to avoid long-distance parallel routing of high-speed signals on the same layer
64. Is there any shielded through hole on the edge of the board and the dividing edge of digital ground, analog ground and protective ground? Are multiple ground planes connected by vias? Is the via distance less than 1 / 20 of the wavelength of the highest frequency signal?
65. Is the signal wiring of surge suppression device short and thick on the surface?
66. Confirm that there is no isolated island, too large slot, or long ground plane crack, thin strip or narrow channel caused by too large or dense through-hole isolation plate
67. Whether the ground vias are placed where the signal line spans more floors (at least two ground planes are required)
i. Power and ground
68. If the power / ground plane is divided, try to avoid high-speed signal crossing on the divided reference plane.
69. Confirm that the power supply and ground can carry enough current. Whether the number of vias meets the bearing requirements (estimation method: 1A / mm line width when the outer copper thickness is 1 oz, 0.5a/mm line width when the inner copper thickness is 0.5a/mm, double the short line current)
70. For power supply with special requirements, whether the voltage drop requirements are met
71. In order to reduce the edge radiation effect of the plane, the 20h principle should be satisfied between the power supply layer and the stratum. (if possible, the more power layers are indented, the better.).
72. If there is an area division, does the divided area not form a loop?
73. Do different power supply planes of adjacent layers avoid overlapping?
74. Is the isolation of protective ground, – 48V ground and GND greater than 2mm?
Is the – 48V ground only a – 48V signal return current, not converged to other places? If you can’t, please explain the reason in the remarks column.
76. Is a protective ground of 10 ~ 20mm arranged near the panel with connector, and the layers are connected by double row staggered holes?
J. prohibited area
78. Under the metal shell device and radiator, there shall be no wiring, copper sheet and through hole that may cause short circuit
79. There shall be no wiring, copper sheet and through hole that may cause short circuit around the mounting screw or washer
80. Whether there is wiring at the reserved position in the design requirements
81. The distance between the inner layer of the nonmetallic hole and the line and the copper foil shall be greater than 0.5mm (20MIL), the outer layer shall be 0.3mm (12mil), and the distance between the inner layer of the axle hole of the single plate pull-out wrench and the line and the copper foil shall be greater than 2mm (80mil)
82. Copper sheet and wire to plate edge are recommended to be more than 2mm, and the minimum is 0.5mm
83, inner layer copper sheet to plate edge 1-2 mm, minimum 0.5mm
k. Pad outgoing line
84. For chip components (package of 0805 and below) installed on two pads, such as resistance and capacitance, it is better to lead out the printed line connected with the pad symmetrically from the center of the pad, and the printed line connected with the pad must have the same width. For outgoing line with line width less than 0.3mm (12mil), this provision may not be considered
85. For pad connected with wide printed wire, it is better to transition through a narrow printed wire in the middle? (0805 and below)
L. silk screen printing
87. Whether the device tag number is missing and whether the location can correctly identify the device
88. Whether the device tag number meets the company’s standard requirements
90. Whether the direction identification of the motherboard and the daughter board corresponds to each other
91. Whether the backplane correctly identifies the slot name, slot number, port name and sheath direction
92. Confirm whether the silk screen required by the design is added correctly
93. Confirm that the anti-static and RF board identifications have been placed (for RF board)
m. Code / barcode
94. Confirm that the PCB code is correct and meets the company’s specifications
95. Confirm that the PCB coding position and layer of the single board are correct (it should be on the top left of plane a, silk screen layer)
96. Confirm that the PCB coding position and layer of the backplane are correct (it should be on the top right of B, the outer copper foil surface)
97. Confirm that there is a bar code laser printing white silk screen marking area
98. Confirm that there are no wires and through holes larger than 0.5mm under the barcode frame
N. through hole
100. On the reflow welding surface, the through hole cannot be designed on the pad. (the distance between the vias of normal window opening and the pad shall be greater than 0.5mm (20MIL), and the distance between the vias covered by green oil and the pad shall be greater than 0.1mm (4mil). Method: open the same net DRC, check the DRC, and then close the same net DRC)
101. The arrangement of vias should not be too dense to avoid large-scale fracture of power supply and ground plane
102. The through hole diameter of the drilling hole should be no less than 1 / 10 of the plate thickness
103. Whether the device placement rate is 100%, and whether the pass rate is 100% (if not, please indicate in the remarks)
104. Whether the dangling line has been adjusted to the minimum, and the reserved dangling line has been confirmed one by one;
105. Whether the process problems fed back by the process department have been checked carefully
p. Large area copper foil
106. For large area copper foil on top and bottom, if there is no special need, grid copper shall be applied (inclined net for single board, orthogonal net for back board, line width 0.3mm (12mil), spacing 0.5mm (20MIL))
107. The component pad in large area of copper foil area shall be designed as a solder pad to avoid false welding; when there is current requirement, the reinforcement of the solder pad shall be widened first, and then the full connection shall be considered
108. When copper is distributed in large area, dead copper (Island) without network connection shall be avoided as far as possible
Q. test point
111. Confirm that the network without test point can be simplified after confirmation
112. Confirm that the test point is not set on the plug-in that is not installed in production
113, whether test via and test pin have fix
114. The spacing rule of test via and test pin should be set to the recommended distance to check the DRC. If there is still DRC, then use the minimum distance setting to check the DRC
116. Confirm that DRC has been adjusted to the minimum, and confirm one by one if DRC cannot be eliminated;
s. Optical positioning point
117. Confirm that there are optical positioning symbols on the PCB with mounting elements
118. Confirm that the optical positioning symbol is not pressed (silk screen and copper foil routing)
120. Confirm that the optical positioning reference symbol of the whole board has been given a coordinate value (it is recommended to place the optical positioning reference symbol in the form of a device), and it is an integral value in mm.
121. For IC with pin center to center distance of 0.5mm and BGA device with center to center distance less than 0.8mm (31 mil), optical positioning points shall be set near the diagonal of the element
t. Welding resistance inspection
123. Whether the through-hole under BGA is treated as oil plug hole
124. Whether the vias other than the test vias have been provided with small windows or oil plug holes
125. Does the window opening of optical positioning point avoid copper and wire exposure
126. Check whether there is copper skin on the power chip, crystal oscillator and other devices that need copper skin for heat dissipation or grounding shielding and open the window correctly. The devices fixed by solder should have green oil to block the large area diffusion of solder
4、 Output processing documents
U. borehole map
127. Is the PCB thickness, layers, silk screen color, warpage and other technical specifications of notes correct
128. Whether the layer name, stacking sequence, medium thickness and copper foil thickness of the laminated drawing are correct; whether impedance control is required and whether the description is accurate. Is the layer name of the overlay consistent with its photo file name
129, turn off the repeat code in the setting table, and set the drilling accuracy to 2-5
130, whether the hole table and drilling file are up-to-date (must be regenerated when changing the hole)
131. Whether there is abnormal hole diameter in the hole table, whether the hole diameter of the crimping piece is correct, and whether the hole diameter tolerance is marked correctly
132. Whether the vias to be plugged are listed separately and marked with “filled vias”
V. light drawing
133. The output of photo file shall be in rs274x format as far as possible, and the precision shall be set to 5:5
134, whether art_aper.txt is up-to-date (274x is unnecessary)
135. Is there any exception report in the log file of the output photo file
136. Edge and island confirmation of negative layer
5、 Complete set of documents
138. PCB file: product model, specification, board code, version number.brd
139. Backing plate design document of backplane: product model, specification, board code, version number, CB [- t / b]. BRD
140, PCB processing file: PCB code.zip (including photo drawing file, aperture table, drilling file and ncdrill.log of each layer; panel also needs to have panel file *. DXF provided by process), and the backplane also needs to attach panel file: PCB code-cb [- t / b]. Zip (including drill.art, *. DRL, ncdrill. Log)
141. Process design document: product model, specification, board code, version No. – gy.doc
142. SMT coordinate file: product model, specification, board code, version No. – smt.txt. (when outputting coordinate file, confirm to select body center, and only when confirming that the origin of all SMD device libraries is device center, select symbol origin.)
143. PCB structure file: product model, specification, board code, version number – mcad.zip (including. DXF and. EMN files provided by structure engineer)
144. Test file: product model, specification, board code, version No. – test.zip (including the coordinate file of testprep.log and untest.lst or *. DRL test point)
145. Filing drawing file: product model and specification – board name – version No
146. Confirm that the information on the front cover and the front page is correct
147. Confirm that the drawing number (corresponding to the sequence allocation of PCB layers) is correct
148. Confirm that the PCB code on the drawing frame is correct