Author: Anthony Desimone, application engineer of ADI company; Michael giancioppo, application engineer

Jesd204b is a recently approved JEDEC standard for serial data interface between converter and digital processor. It is the third generation standard and solves some defects of the previous version. The advantages of the interface include less circuit board space for data interface routing, lower requirements for establishing and maintaining timing, and smaller packaging of converters and logic devices. New analog / digital converters from several suppliers use this interface, such as ADI’s ad9250.

Compared with the existing interface formats and protocols, the jesd204b interface is more complex and subtle. Some difficulties must be overcome to realize its advantages. Like any other standard, to make this interface more popular than common interfaces such as single data rate or double data rate CMOS / LVDS, it must work seamlessly. Although the jesd204b standard was developed by JEDEC, some specific information still needs to be clarified or may be scattered in multiple references. In addition, if there is a concise guide that can outline the standard, working principle and how to troubleshoot, it will undoubtedly be very helpful to users.

This paper explains the interface between ADC and FPGA of jesd204b standard, how to judge whether it works normally, and perhaps more importantly, how to eliminate faults when there are problems. The troubleshooting technology discussed in this paper can use common test and measurement equipment, including oscilloscope, logic analyzer and Xilinx ® Chipscope or Altera for ® Signaltap and other software tools. At the same time, the interface signal transmission is clarified, so that the visualization of signal transmission can be realized by one or more methods.

Jesd204b overview

Jesd204b standard provides a method to interface one or more data converters with digital signal processor devices (usually ADC or DAC and FPGA interface), which is a higher speed serial interface compared with the usual parallel data transmission. The interface speeds up to 12.5 Gbps / channel and uses frame serial data links with embedded clocks and aligned characters. It reduces the number of routing between devices, reduces the requirements of routing matching, and eliminates the problem of establishing and maintaining timing constraints, so as to simplify the implementation of data interface of high-speed converter. Since the link needs to be established before data transmission, there are new challenges. New technologies must be adopted to determine whether the interface works normally and what to do in case of interface failure.

The jesd204b interface establishes the synchronization link through three stages: code group synchronization (CGS), initial channel synchronization (ILAS) and data transmission. The link requires the following signals: a shared reference clock (device clock), at least one differential CML physical data electrical connection (referred to as “channel”), and at least one other synchronization signal (sync ~ and possibly sysref). Which signals to use depends on the subclass:

  • Subclass 0 uses device clock, channel, and sync ~.
  • Subclass 1 uses device clock, channel, sync ~ and sysref;
  • Subclass 2 uses device clocks, channels, and sync ~.

Subclass 0 is sufficient to meet the requirements in many cases, so it is the focus of this paper. Subclasses 1 and 2 provide methods to establish deterministic delay, which is very important in applications requiring synchronization of multiple devices or system synchronization or fixed delay. For example, an event of a system requires a known sampling edge, or an event must respond to an input signal within a specified time.

Figure 1 shows a simplified jesd204b link from a transmitting device (ADC) to a receiving device (FPGA), and data is transmitted from an ADC through a channel.

Although the jesd204b specification has many variables, some variables are particularly important for link establishment. These key variables are as follows (Note: these values are usually expressed as “x − 1”):

  • M: Number of converters.
  • 50: Number of physical channels.
  • F: Number of 8-bit bytes per frame.
  • K: The number of frames per multiframe.

UN and N ‘: respectively represent the resolution of the converter and the number of bits used for each sample (multiple of 4). The value of n ‘is equal to the n value plus the number of control and fill data bits.

Subclass 0: synchronization step

Code group synchronization (CGS) phase

The most important part of the CGS phase that can be observed on the link is shown in Figure 2. The five highlighted points in the figure are described as follows.

  • The receiver sends a synchronization request by pulling down the sync ~ pin.
  • The transceiver starts with the next symbol and sends the undisturbed / K28 5 / symbols (10 bits per symbol).
  • When the receiver receives at least 4 error free continuous / K28 5 / when the symbol is synchronized, then pull the sync ~ pin high.
  • The receiver must receive at least 4 error free 8B / 10B characters, otherwise the synchronization will fail and the link will remain in the CGS stage.
  • CGS phase ends and ILAS phase begins.

/K28. 5 / character is also called / K / in jesd204b standard, as shown in Figure 3. The standard requires DC balance. Using 8B / 10B coding, balanced sequences containing equal amounts of 1 and 0 on average can be realized. Each 8B10B character may have a positive (more than 1) or negative (more than 0) deviation. The parity of the current character is determined by the polarity deviation of the previously transmitted characters, which is usually realized by alternately transmitting positive parity words and negative parity words. / K28 is shown in the figure 5 / two polarities of the symbol.

pYYBAGHbpByAKNzHAAXAzyb9J3c628.png

Figure 1 Jesd204b link diagram: an ADC interfaces with FPGA through one channel

pYYBAGHbpCSAF9AcAAJEvXpUi7s364.png

Figure 2 Logic output of jesd204b subclass 0 link signal in CGS phase (assuming that there are two channels and one device contains two ADCs)

pYYBAGHbpCuAXZbqAAJjnOsqlQU196.png

Figure 3 K28. Logical output of 5 characters and how it propagates through jesd204b TX signal path

Focus on the following points:

  • The serial value represents the 10 bit logic level transmitted through the channel, which can be seen by the oscilloscope measuring the physical interface.
  • 8B / 10B value represents the logic value (10 bits) transmitted through the channel, which can be seen by the logic analyzer measuring the physical interface.
  • Data value and data logic represent the logic level of symbols in jesd204b transceiver module before 8B / 10B coding, which can be seen through FPGA logic analysis tools such as Xilinx chipscope or Altera signaltap.
  • The symbol represents the hexadecimal value of the character to be sent. Pay attention to the parity of the PHY layer.
  • The character represents the jesd204b character referred to in the JEDEC specification.

ILAS phase

The ILAS phase has four multi frames, allowing the receiver to align channels from all links and verify link parameters. In order to reconcile different lengths of routing and character skew caused by the receiver, the channels must be aligned. Four multiple frames are closely connected (Fig. 4). ILAS always transmits without scrambling whether the scrambling link parameter is enabled or not.

After the sync signal changes from low level to high level, it enters the ILAS stage. After a complete multi frame is tracked inside the sending module (inside the ADC), it starts to send four multi frames. Fill data is inserted into the required characters to transmit the complete multi frame (Fig. 4). The 4 multiframes include:

  • Multi frame 1: with / R / character [K28 Start with / A / character [K28 3] end.
  • Multi frame 2: start with / R / character, followed by / Q / [K28 4] character, followed by 14 link configuration parameters configured with 8-bit words (Table 1), and finally ended with / A /.
  • Multiframe 3: same as multiframe 1.
  • Multiframe 4: same as multiframe 1.
  • The frame length can be calculated using the jesd204b parameters:

(S) × (1 / sampling rate).

meaning:

(number of samples / converter / frame) × (1 / sample rate)

Example:

A converter with a sampling rate of 250 MSPs and one sample per converter per frame (Note: in this example, “s” is 0 because it is encoded as binary value – 1), and its frame length is 4 ns.

poYBAGHbpFSAGNdgAAA0e3LH4G4144.png (1)

The multi frame length can be calculated using the jesd204b parameters:

poYBAGHbpFuAYmLuAABAIOU3M4k366.png (2)

meaning:

(number of samples / converter / frame) × (frames / multiple frames) × (1 / sampling rate)

Example:

A converter with a sampling rate of 250 MSPs, one sample per converter per frame and 32 frames per multi frame has a multi frame length of 128 ns.

poYBAGHbpGWADiy1AABJ7dpkuaM269.png (3)

Data phase (enable character replacement)

In the data transmission phase, frame alignment is monitored by controlling characters. Performs character replacement at the end of the frame. In the data phase, data or frame alignment does not incur additional overhead. Character replacement allows aligned characters to be sent at the frame boundary, only if the last character of the current frame can be replaced with the last character of the previous frame. This facilitates (occasionally) confirmation that the alignment has not changed since the ILAS sequence.

Character replacement is performed on the transmitter when:

  • If scrambling is disabled, the last 8-bit word of a frame or multiple frames is equal to the 8-bit word of the previous frame.
  • If scrambling is enabled, the last 8-bit word of the multi frame is equal to 0x7c, or the last 8-bit word of the frame is equal to 0xfc.

The transmitter and receiver each maintain a local multi frame counter (LMFC), which continuously counts to (f) × K) − 1, then go back to “0” and start counting again (ignoring the internal word width). Send a common (source) sysref to all transmitters and receivers. These devices use sysref to reset their LMFC, so that all LMFC should be synchronized with each other (within one clock cycle).

After releasing sync (which can be seen by all devices), the transmitter starts ILAS the next time (TX) LMFC goes back to 0. If f × If K is set appropriately and is greater than (transmitter encoding time) + (line propagation time) + (receiver decoding time), the received data will be transmitted from the SerDes of the receiver before the next LMFC. The receiver will feed the data into the FIFO and then output the data at the next (Rx) LMFC boundary. This known relationship between the SerDes input of the transmitter and the FIFO output of the receiver is called deterministic delay.

poYBAGHbpDaAJPSIAAGdmtzLbZg772.png

Figure 4 Logic output of jesd204b subclass 0 link signal in ILAS stage

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Figure 5/ K / character [K28 5, / R / character [K28 0, / A / character [K28 3] and / Q / characters [K28 4] FIG

Table 1 Config table of ILAS multi frame 2 (14 jesd204b configuration parameters 8-bit words)

What can go wrong?

Jesd204b can be said to be a complex interface standard with many subtleties in operation. In order to find out the reason why it does not work properly, it is necessary to have a good understanding of the possible situations:

Fall into CGS mode: if sync keeps logic low level; Or pulse high-level duration is less than 4 multiple frames:

Check the circuit board without power on:

  • Sysref and sync ~ signals shall be DC coupled.
  • When the circuit board is not powered on, check whether the circuit board sync ~ connection from sync ~ source (usually from FPGA or DAC) to sync ~ input (usually ADC or FPGA) is good and has low impedance.
  • Make sure that the pull-down or pull-up resistance is not the dominant factor of signal transmission. For example, too small value or short circuit will lead to failure to drive correctly.
  • Confirm that the differential pair routing (and cable, if used) of jesd204b link matches.
  • Confirm that the differential impedance of the wiring is 100 Ω.

Check the circuit board and power on:

  • If there is a buffer / converter in the sync path, make sure it works properly.
  • Confirm that the sync ~ source and on-board circuit (sync + and sync -, if differential) are configured correctly to generate a logic level that meets the requirements of sync ~ receiving device. If the logic levels are incompatible, check the source and receive configurations to find out the problem, otherwise consult the device manufacturer.
  • Confirm that the jesd204b serial transmitter and board circuit are configured correctly to generate the correct logic level meeting the requirements of jesd204b serial data receiver. If the logic levels are incompatible, check the source and receiving configuration of the circuit to find out the problem. Otherwise, consult the device manufacturer.

Check sync ~ signal:

  • If sync ~ is static logic level, the link will stay in CGS phase. There may be a problem with the transmitted data, or the jesd204b receiver does not decode the sample correctly. Confirm that the / K / character is sent, confirm the receiving configuration settings, confirm the sync ~ source, check the board circuit, consider driving the sync ~ signal and force the link to enter the ILAS mode, so as to find out the problems of the link receiver and transceiver. Otherwise, consult the device manufacturer.
  • If sync ~ is static logic high level, confirm whether the source device has correctly configured sync ~ logic level. Check the pull-up and pull-down resistance.
  • If the sync ~ pulse becomes high and then returns to the logic low state and lasts less than 6 multi frame cycles, the jesd204b link will advance from the CGS phase to the ILAS phase, but will stay in the later phase. This may mean that the / K / character is correct and the basic function of CDR is normal. See the ILAS troubleshooting section.
  • If sync ~ becomes high and the duration is greater than 6 multi frame cycles, the link will advance from ILAS stage to data stage, but will fail in the later stage; Refer to the “data phase” section for troubleshooting tips.

Check serial data

  • Verify that the data speed of the transceiver is the same as the expected rate of the receiver.
  • Measure the channel with a high impedance probe (differential probe if possible); If the characters look wrong, ensure that the channel differential routing matches, the return path on the PCB is not interrupted, and the device is correctly welded to the PCA. Unlike the (seemingly) random characters in ILAS and data stages, CGS characters are easy to recognize on the oscilloscope (if an oscilloscope with high enough speed is used).
  • Verify the / K / character with a high impedance probe.

■ if the / K / character is correct, it indicates that the transceiver end of the link is working normally.

■ if the / K / character is incorrect, it indicates that there is a problem with the transceiver device or circuit board channel signal.

  • In case of DC coupling, confirm that the common mode voltage of the transmitter and receiver is within the required range of the device.

■ depending on the implementation, the transmitter common mode voltage range may be 490 MV to 1135 MV.

■ depending on the implementation, the receiver common mode voltage range may be 490 MV to 1300 MV.

  • Confirm the transmitter CML differential voltage on the data channel (note that the CML differential voltage is equal to twice the voltage swing on each side of the signal).

■ transmitter CML differential voltage ranges from 0.5 V P-P to 1.0 V P-P for speeds up to 3.125 Gbps.

■ transmitter CML differential voltage ranges from 0.4 V P-P to 0.75 V P-P for speeds up to 6.374 Gbps.

■ transmitter CML differential voltage ranges from 0.360 V P-P to 0.770 V P-P for speeds up to 12.5 Gbps.

  • Confirm the receiver CML differential voltage on the data channel (note that the CML differential voltage is equal to twice the voltage swing on each side of the signal).

■ for speeds up to 3.125 Gbps, the receiver CML differential voltage range is 0.175 V P-P to 1.0 V p-p.

■ for speeds up to 6.374 Gbps, the receiver CML differential voltage range is 0.125 V P-P to 0.75 V p-p.

■ for speeds up to 12.5 Gbps, the receiver CML differential voltage range is 0.110 V P-P to 1.05 V p-p.

  • If the pre emphasis option exists, enable it and observe the data signal on the data path.
  • Confirm that the M and L values of the transmitter and receiver are consistent, otherwise the data rate may not match. For example, the expected serial interface data rate in the case of M = 2 and L = 2 is half that in the case of M = 2 and L = 1.
  • Ensure that the device clocks entering the transmitter and receiver are phase locked and the frequency is correct.

If sync becomes high and lasts for about 4 multiple frames, stay in ILAS mode:

  • Link parameter conflict

■ confirm that the link parameters are not offset by 1 (many parameters are specified as the value minus 1).

■ confirm that the multi frame transmission of ILAS is correct, and confirm that the link parameters of transceiver, receiver and the second multi frame transmission of ILAS are correct.

■ calculate the expected ILAS length (TFrame, tmultiframe, 4 × Tmultiframe), confirm that ILAS has attempted about 4 multiple frames.

  • Confirm that all channels work normally. Ensure that there are no multi-channel / multi link conflicts.

Enter the data phase, but the link will be reset occasionally (return to CGS and ILAS phase first, and then enter the data phase):

  • The establishment and holding time of periodic or bandgap periodic sysref or sync ~ signal is invalid.
  • Link parameters conflict.
  • Character substitution conflict.
  • Scrambling problem (if enabled).
  • Channel data corruption, noise or jitter may force the eye diagram to close.
  • Excessive jitter of spurious clock or device clock

Other general tips for troubleshooting link faults:

  • Run the converter and link at the lowest speed allowed so that low bandwidth measuring instruments that are easily available can be used.
  • Set the minimum m, l, K, s combination allowed
  • Use test mode when possible
  • Use subclass 0 to troubleshoot
  • Disable scrambling when troubleshooting

This troubleshooting guide is not exhaustive, but it provides a good basic framework for engineers who use the jesd204b link and want to learn more.

The above is an overview of the jesd204b specification and provides practical information related to the link. It is hoped that engineers involved in this latest performance interface standard can benefit from it and help in troubleshooting.

Introduction to the author

Anthony Desimone is an application engineer in the high-speed converter Department of ADI. He holds a bachelor’s degree in electrical engineering from the University of Massachusetts Lowell and a master’s degree in electrical engineering from Tufts University.

Michael giancioppo is an application engineer in the Application Technology Department of ADI company. He received his bachelor’s degree in electrical engineering / computer systems engineering from the University of Massachusetts Amherst in 1981.

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