Ads41bx9 is a member of the ultra-low power ads4xxx analog-to-digital converter (ADC) family with integrated analog input buffer. These devices use innovative design techniques to achieve high dynamic performance and ultra-low power consumption. The analog input pins have buffers, which have the advantage of maintaining constant performance and input impedance over a wide frequency range. The device is very suitable for multicarrier, broadband communication applications such as PA linearization.

The ads41bx9 has functions such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated DC offset correction loop can be used to estimate and eliminate ADC offset. At lower sampling rates, the ADC automatically reduces power proportionally in performance without loss.

The device supports double data rate (DDR), low voltage differential signal (LVDS) and parallel CMOS digital output interface. The low data rate at the ddrlvds interface (up to 500mbps) makes it possible to use low-cost field programmable gate array (FPGA) receivers. The device can be used to further reduce power consumption in low swing LVDS mode. The strength of the LVDS output buffer can also be increased to support 50- Ω Differential matching.

These devices are packaged in a compact vqfn-48 package over the entire industrial temperature range (- 40 ℃) ° C to + 85 ° C) Specify.

Function and performance analysis of ultra low power ads41bx9 ADC


Ads41b49: 14 bit, 250msps

Ads41b29: 12 bit, 250msps

Integrated high impedance

Analog input buffer:

Input capacitance: 2pF

Input resistance of 200 MHz: 3K Ω

Maximum sampling rate: 250msps

Ultra low power consumption:

1.8-V analog power supply: 180 MW

3.3-V buffer power supply: 96 MW

High dynamic performance:

Signal to noise ratio: 69dbfs at 170 MHz

SFDR: 82.5dbc at 170 MHz

Output interface:

Double data rate (DDR) LVDS with programmable swing and strength:

Standard swing: 350 MV

Low swing: 200mV

Default strength: 100 Ω terminal

2X strength: 50 Ω terminal

The 1.8-vcmos parallel interface is also supported

For SNR programmable gain, SFDR tradeoff

DC offset correction

Support low input clock amplitude

Package: vqfn-48 (7mm) × 7MM)

Editor in charge: GT

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