Ads4125 is a low sampling rate variant of ads41xx series ADC. These devices use innovative design methods to achieve high dynamic performance and low power consumption (1.8V power supply). They are very suitable for multi carrier, large bandwidth communication applications.

The ads4125 has a fine gain option, which can be used to improve SFDR performance in a low full-scale input range, especially at high input frequencies. These devices include a DC offset correction loop, which can be used to eliminate ADC offset. At lower sampling rate, the power consumption of ADC will be reduced automatically without performance loss.

Ads4125 adopts compact qfn-48 package, and its technical specification is for industrial temperature range (- 40 ℃) ° C to + 85 ° C) It was drafted.

Function and performance analysis of ads4125 ADC

characteristic

Ultra low power consumption (1.8V single power supply)

Total power consumption of 103mw (at 65msps sampling rate)

Total power consumption of 153mw (at 125msps sampling rate)

High dynamic performance:

SNR: 72.2dbfs (at 170mhz)

* SFDR: 81dbc (at 170mhz)

The power is adjusted dynamically with the sampling rate

Output interface:

Double data rate (DDR) LVDS with programmable swing and strength standard swing: 350mV low swing: 200mV default strength: 100 Ω Terminal 2x strength: 50 Ω terminal

Also supports 1.8V parallel CMOS interface

Programmable gain up to 6dB for SNR / SFDR tradeoff

DC offset correction

Support low input clock amplitude as low as 200mvpp

Package: qfn-48 (7mmx7mm)

Editor in charge: GT

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