summary

With the rapid increase of the design scale and the continuous improvement of the design process complexity, especially the scale of parasitic devices in the post analog circuit brought by the complex FinFET technology, the traditional SPICE simulation tool has encountered unprecedented challenges in functional verification. Firstly, the simulation time is too long, and many designs have to run for several days or even weeks; secondly, the simulation capacity is huge, which has exceeded the processing capacity of traditional simulation tools; moreover, the number of PVT process angles is more and more, which can not be fully and accurately verified, which greatly increases the design risk.

The existing post simulation tools in the market can not meet the needs of the industry. On the one hand, the speed can not meet the requirements, and it takes weeks or even months for some post simulation circuits; on the other hand, the accuracy can not meet the requirements, because the post simulation tools may adopt more radical reduction technology to improve the performance, resulting in the simulation results can not be accepted; finally, it is not convenient for users to use and need to set different circuit types In order to get better speed and accuracy.

Empyrean Alps (accurate large capacity parallel spice) is a new generation of high-speed and high-precision parallel transistor level circuit simulation tool, which can break through the capacity and speed bottlenecks encountered in the verification of large-scale circuits under the premise of maintaining 100% spice accuracy. Alps can handle the design of tens of millions of components (especially for post analog circuits). It adopts unique intelligent matrix solver and parallel technology, which greatly improves the simulation speed. Compared with other commercial parallel spice simulators, Alps has a speedup of 3-8 times.

Function, advantage and characteristic analysis of empyrean Alps

Functions and advantages:

SPICE circuit simulation

》Simulation capacity of 100m device scale

The unique multi-core parallel simulation technology maintains a good linear speedup, and can achieve 3-8 times speedup for commercial parallel spice simulator

Co SIM supporting mixed simulation and industry leading digital simulator

For power management circuits, it has excellent convergence and performance

Perfect circuit automatic static and dynamic inspection to help find potential design problems

Support save / recover breakpoint copy function p unique encryption tool to protect your intellectual property rights

Easy integration into mainstream IC design platform and mainstream IC analysis and optimization tools

The model is certified by the international leading foundry

Support the latest 5nm process

Matrix solution

More than 10 matrix solving methods are integrated to ensure the stable convergence of various types of circuits

Intelligent matrix solver, precision lossless, maintain the physical topology structure, the performance of the industry-leading matrix solver can reach 5-10 times the speedup

Function:

1. Accuracy: Alps has complete spice accuracy, and does not use any model simplification technology to solve the whole circuit equation. The simulation results are verified by silicon measurement.

2. Speed: Alps adopts intelligent matrix solver with lossless precision for post analog circuit, uses advanced matrix solving technology and multi thread parallel algorithm. Compared with the traditional spice simulator, it can accelerate 5-10 times. For the leading commercial parallel spice simulator, it has 3-8 times speedup.

3. Capacity: Alps adopts a unique memory management method. The circuit simulation capacity of 100m device scale can almost reach the capacity similar to fast spice while ensuring the simulation accuracy.

characteristic:

1. Comprehensive circuit simulation analysis:

Support common circuit analysis types such as OP, DC, tran, AC, PZ, STB, noise, transient noise and multi scan

Provide complete corner analysis

Support Monte Carlo analysis and fast Monte Carlo analysis

2. Supported data and platforms

Support mainstream transistor model and modeling language

• BSIM3, BSIM4, BSIMSOI, BSIMCMG, PSP, MOSVAR,MOS1, MOS3, TFT, HiSim_ HV, MOS20 • BJT, JFET, DIODE

• S-element/Nport

Passive components and power supply

Support hardware description language verilog-a, verilog

3. Process integration

• Industry leading EDA design environment

• Command line mode

4. Supported platforms

X86 64-bit:

• Red Hat Enterprise V5, and V6

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