The basic structure of Xilinx FPGA is the same, which is mainly composed of 6 parts: programmable input / output unit, basic programmable logic unit, embedded block ram, rich wiring resources, underlying embedded functional unit and embedded special hard core.

However, with the development of semiconductor technology, the logic capacity of FPGA is richer and faster, and more and more hard cores are embedded, such as ARM processor, PCIe, Ethernet, etc. In terms of process technology, Xilinx’s 7-series FPGA adopts 28 nm process, ultrascale adopts 20 nm and ultrascale + adopts 16 nm. The available resources of each generation of process are twice that of the previous generation.

Xilinx’s FPGA is based on SRAM LUT look up table technology, so it needs to be reconfigured after power on. Read from the external nonvolatile memory and load it into the internal configuration SRAM through the configuration controller. FPGA structure: programmable I / O (input / output unit). Programmable I / O supports different IO pin configurations: IO standard, single ended or differential, voltage conversion rate and output strength, pull-up or pull-down resistance, numerical control impedance (DCI). Iodelay element can be used for output delay.

Configurable logic block CLB (configure logic block) refers to the circuit that realizes various logic functions and is the basic logic unit of Xilinx. In Xilinx FPGA, each configurable logic block contains 2 slices. Each slice consists of lookup table, register, carry chain and multiple majority selectors. Slice has two different logic slices: slicem and slicel. Slicem has a multifunctional LUT, which can be configured as shift register, or ROM and ram. Each register in the logic chip can be configured for latch use.

FPGA will further expand its territory in new fields such as cloud computing

Wiring resources are used to connect all units inside the FPGA, and the length and process of the wiring determine the driving ability and transmission speed of the signal on the wiring. There are abundant wiring resources inside the FPGA chip, which are divided into four different categories according to the process, length, width and distribution position.

The first is the global wiring resource, which is used for the wiring of the internal global clock and reset / set of the chip; The second type is long-term resources, which are used to complete the high-speed signal between banks; The third category is short-term resources, which are used to complete the logical interconnection and wiring between basic logic units; The fourth category is distributed wiring resources, which are used for proprietary clock, reset and other control signal lines.

Clock resources are divided into global clock resources, regional clock resources and I / o clock resources. (1) Global clock network is a global routing resource, which can ensure that the delay of clock signal reaching each target logic unit is basically the same. (2) The regional clock network is a group of clock networks independent of the global clock network. (3) I / o clock resources can be used for local I / O serializer / deserializer circuit design. It is especially useful for source synchronization interface design.

There are two types of embedded memory in Xilinx FPGA: dedicated block RAM (Bram) and LUT that can be configured as distributed ram. Bram (block RAM) is a dual port RAM. The number depends on the device. Each virtex-4 Bram can store 18kbit data and support synchronous read-write operations. The two ports are symmetrical and completely independent and share data. Each port can change its bit width and depth as needed. Bram can be configured as single port RAM, dual port RAM, content addressable memory (CAM), FIFO, etc. Bram provides special control logic to realize synchronous / asynchronous FIFO. The control logic such as counter, comparator and status mark will not occupy additional CLB resources.

In FIFO mode, port a of Bram is a read port and port B is a write port. The data flow operation is automatic. Users do not have to care about the address sequence of Bram. Wrcount and rdcount are exported when required by special applications. The user needs to detect the full and empty tags. These two tag values can be set and configured anywhere in the FIFO address segment.

In addition to the above resources and functional modules, FPGA also has clock management (MMCM): digital clock management module (DCM), phase matching clock divider (PCMD), DSP module, etc. DSP module can provide high-performance and low-power computing unit. It can realize multiplication accumulation unit. It also provides a special transceiver module to realize the function of serializer / deserializer (SerDes), such as rocketoio module, Ethernet MAC module and arm core.

In short, as the internal resources of FPGA will become more and more abundant, it will not only be widely used in many fields such as network, telecommunications, medical treatment and industry, but also further expand its territory in new fields such as data center and cloud computing.

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